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| High Performance E2CMOS(R) In-System Programmable Logic FEATURES x High-performance, E2CMOS 3.3-V & 5-V CPLD families x Flexible architecture for rapid logic designs ispMACHTM 4A CPLD Family x x x x x x x x -- Excellent First-Time-FitTM and refit feature -- SpeedLockingTM performance for guaranteed fixed timing -- Central, input and output switch matrices for 100% routability and 100% pin-out retention High speed -- 5.0ns tPD Commercial and 7.5ns tPD Industrial -- 182MHz fCNT 32 to 512 macrocells; 32 to 768 registers 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages Flexible architecture for a wide range of design styles -- D/T registers and latches -- Synchronous or asynchronous mode -- Dedicated input registers -- Programmable polarity -- Reset/ preset swapping Advanced capabilities for easy system integration -- 3.3-V & 5-V JEDEC-compliant operations -- JTAG (IEEE 1149.1) compliant for boundary scan testing -- 3.3-V & 5-V JTAG in-system programming -- PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades) -- Safe for mixed supply voltage system designs -- Programmable pull-up or Bus-FriendlyTM inputs and I/Os -- Hot-socketing -- Programmable security bit -- Individual output slew rate control Advanced E2CMOS process provides high-performance, cost-effective solutions Supported by ispDesignEXPERTTM software for rapid logic development -- Supports HDL design methodologies with results optimized for ispMACH 4A -- Flexibility to adapt to user requirements -- Software partnerships that ensure customer success Lattice and third-party hardware programming support -- LatticePROTM software for in-system programmability support on PCs and automated test equipment -- Programming support on all major programmers including Data I/O, BP Microsystems, Advin, and System General Publication# ISPM4A Amendment/0 Rev: D Issue Date: August 2000 Table 1. ispMACH 4A Device Features 3.3 V Devices Feature Macrocells User I/O options tPD (ns) fCNT (MHz) tCOS (ns) tSS (ns) Static Power (mA) JTAG Compliant PCI Compliant 5 V Devices Feature Macrocells User I/O options tPD (ns) fCNT (MHz) tCOS (ns) tSS (ns) Static Power (mA) JTAG Compliant PCI Compliant M4A5-322 32 32 5.0 182 4.0 3.0 20 Yes Yes M4A5-642 64 32 5.5 167 4.0 3.5 25 Yes Yes M4A5-962 96 48 5.5 167 4.0 3.5 40 Yes Yes M4A5-1282 128 64 5.5 167 4.0 3.5 55 Yes Yes M4A5-1921 192 96 6.0 160 4.5 3.5 74 Yes Yes M4A5-2562 256 128 6.5 154 5.0 3.5 110 Yes Yes M4A3-322 32 32 5.0 182 4.0 3.0 20 Yes Yes M4A3-642 64 32/641 5.5 167 4.0 3.5 25/521 Yes Yes M4A3-962 96 48 5.5 167 4.0 3.5 40 Yes Yes M4A3-1282 128 64 5.5 167 4.0 3.5 55 Yes Yes M4A3-1922 192 96 6.0 160 4.5 3.5 85 Yes Yes M4A3-256 256 1282/1601/1921 5.53 167 4.0 3.5 1102/1501 Yes Yes M4A3-3842 384 160/192 6.5 154 4.5 3.5 149/155 Yes Yes M4A3-5121 512 160/192/256 7.5 125 5.5 5.0 179 Yes Yes Notes: 1. Advance information. Please contact a Lattice sales representative for details on availability. 2. Preliminary information. 3. M4A3-256/128 available now in 5.5ns. Contact factory for availability of 7.5ns M4A3-256/160 and M4A3-256/192 2 ispMACH 4A Family GENERAL DESCRIPTION The ispMACHTM 4A family from Lattice offers an exceptionally flexible architecture and delivers a superior Complex Programmable Logic Device (CPLD) solution of easy-to-use silicon products and software tools. The overall benefits for users are a guaranteed and predictable CPLD solution, faster time-to-market, greater flexibility and lower cost. The ispMACH 4A devices offer densities ranging from 32 to 512 macrocells with 100% utilization and 100% pin-out retention. The ispMACH 4A families offer 5-V (M4A5-xxx) and 3.3-V (M4A3-xxx) operation. ispMACH 4A products are 5-V or 3.3-V in-system programmable through the JTAG (IEEE Std. 1149.1) interface. JTAG boundary scan testing also allows product testability on automated test equipment for device connectivity. All ispMACH 4A family members deliver First-Time-Fit and easy system integration with pin-out retention after any design change and refit. For both 3.3-V and 5-V operation, ispMACH 4A products can deliver guaranteed fixed timing as fast as 5.0 ns tPD and 182 MHz fCNT through the SpeedLocking feature when using up to 20 product terms per output (Table 2). Table 2. ispMACH 4A Speed Grades Speed Grade Device M4A3-323 M4A5-323 M4A3-64/323 M4A5-64/323 M4A3-64/642 M4A3-963 M4A5-963 M4A3-1283 M4A5-1283 M4A3-1923 M4A5-1922 M4A3-256/1283 M4A5-256/1283 M4A3-256/1922 M4A3-256/1602 M4A3-3842 M4A3-5122 Notes: 1. C = Commercial, C C C -5 C C C C C C C C -55 -6 -65 -7 C, I C, I C, I C, I C, I C, I C, I C C -10 C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I C, I -12 I I I I I I I I I C, I C, I I I -14 I = Industrial 2. Advance information. Please contact a Lattice sales representative for details on availability. 3. Preliminary information. ispMACH 4A Family 3 The ispMACH 4A family offers 20 density-I/O combinations in Thin Quad Flat Pack (TQFP), Plastic Quad Flat Pack (PQFP), Plastic Leaded Chip Carrier (PLCC), Ball Grid Array (BGA), finepitch BGA (fpBGA), and chip-array BGA (caBGA) packages ranging from 44 to 388 pins (Table 3). It also offers I/O safety features for mixed-voltage designs so that the 3.3-V devices can accept 5-V inputs, and 5-V devices do not overdrive 3.3-V inputs. Additional features include BusFriendly inputs and I/Os, a programmable power-down mode for extra power savings and individual output slew rate control for the highest speed transition or for the lowest noise transition. Table 3. ispMACH 4A Package and I/O Options (Number of I/Os and dedicated inputs in Table) 3.3 V Devices Package 44-pin PLCC 44-pin TQFP 48-pin TQFP 100-pin TQFP 100-pin PQFP 100-ball caBGA 144-pin TQFP 144-ball fpBGA 208-pin PQFP 256-ball fpBGA 256-ball BGA 388-ball fpBGA 5 V Devices Package 44-pin PLCC 44-pin TQFP 48-pin TQFP 100-pin TQFP 100-pin PQFP 144-pin TQFP 208-pin PQFP 256-ball BGA M4A5-322 32+2 32+2 32+2 M4A5-642 32+2 32+2 32+2 48+8 64+6 64+6 96+16 128+14 128+14 M4A5-962 M4A5-1282 M4A5-1921 M4A5-2562 M4A3-322 32+2 32+2 32+2 M4A3-64 32+22 32+22 32+22 64+61 48+8 64+62 64+62 64+61 96+162 96+161 128+142, 1601 128+142, 1921 128+142 160 192 192 256 160 192 M4A3-962 M4A3-128 M4A3-192 M4A3-256 M4A3-3841 M4A3-5121 Note: 1. Advance information. Please contact a Lattice sales representative for details on availability. 2. Preliminary information. 4 ispMACH 4A Family FUNCTIONAL DESCRIPTION The fundamental architecture of ispMACH 4A devices (Figure 1) consists of multiple, optimized PAL(R) blocks interconnected by a central switch matrix. The central switch matrix allows communication between PAL blocks and routes inputs to the PAL blocks. Together, the PAL blocks and central switch matrix allow the logic designer to create large designs in a single device instead of having to use multiple devices. The key to being able to make effective use of these devices lies in the interconnect schemes. In the ispMACH 4A architecture, the macrocells are flexibly coupled to the product terms through the logic allocator, and the I/O pins are flexibly coupled to the macrocells due to the output switch matrix. In addition, more input routing options are provided by the input switch matrix. These resources provide the flexibility needed to fit designs efficiently. PAL Block 4 Clock Generator Clock/Input Pins Note 3 Note 2 Central Switch Matrix Logic Array Input Switch Matrix Logic 16 Output/ Allocator Buried with XOR Macrocells 16 16 8 Note 1 Dedicated Input Pins 16 PAL Block PAL Block I/O Cells 33/ 34/ 36 Output Switch Matrix I/O Pins I/O Pins I/O Pins 17466G-001 Figure 1. ispMACH 4A Block Diagram and PAL Block Structure Notes: 1. 16 for ispMACH 4A devices with 1:1 macrocell-I/O cell ratio (see next page). 2. Block clocks do not go to I/O cells in M4A(3,5)-32/32. 3. M4A(3,5)-192, M4A(3,5)-256, M4A3-384, and M4A3-512 have dedicated clock pins which cannot be used as inputs and do not connect to the central switch matrix. ispMACH 4A Family 5 Table 4. Architectural Summary of ispMACH 4A devices ispMACH 4A Devices M4A3-64/32, M4A5-64/32 M4A3-96/48, M4A5-96/48 M4A3-128/64, M4A5-128/64 M4A3-192/96, M4A5-192/96 M4A3-256/128, M4A5-256/128 M4A3-384 M4A3-512 Macrocell-I/O Cell Ratio Input Switch Matrix Input Registers Central Switch Matrix Output Switch Matrix 2:1 Yes Yes Yes Yes M4A3-32/32 M4A5-32/32 M4A3-64/64 M4A3-256/160 M4A3-256/192 1:1 Yes1 No Yes Yes The Macrocell-I/O cell ratio is defined as the number of macrocells versus the number of I/O cells internally in a PAL block (Table 4). The central switch matrix takes all dedicated inputs and signals from the input switch matrices and routes them as needed to the PAL blocks. Feedback signals that return to the same PAL block still must go through the central switch matrix. This mechanism ensures that PAL blocks in ispMACH 4A devices communicate with each other with consistent, predictable delays. The central switch matrix makes a ispMACH 4A device more advanced than simply several PAL devices on a single chip. It allows the designer to think of the device not as a collection of blocks, but as a single programmable device; the software partitions the design into PAL blocks through the central switch matrix so that the designer does not have to be concerned with the internal architecture of the device. Each PAL block consists of: x x x x x x x Product-term array Logic allocator Macrocells Output switch matrix I/O cells Input switch matrix Clock generator Notes: 1. M4A3-64/64 internal switch matrix functionality embedded in central switch matrix. 6 ispMACH 4A Family Product-Term Array The product-term array consists of a number of product terms that form the basis of the logic being implemented. The inputs to the AND gates come from the central switch matrix (Table 5), and are provided in both true and complement forms for efficient logic implementation. Table 5. PAL Block Inputs Device M4A3-32/32 and M4A5-32/32 M4A3-64/32 and M4A5-64/32 M4A3-64/64 M4A3-96/48 and M4A5-96/48 M4A3-128/64 and M4A5-128/64 M4A3-192/96 and M4A5-192/96 M4A3-256/128 and M4A5-256/128 M4A3-256/160 and M4A3-256/192 M4A3-384 M4A3-512 Number of Inputs to PAL Block 33 33 33 33 33 34 34 36 36 36 Logic Allocator Within the logic allocator, product terms are allocated to macrocells in "product term clusters." The availability and distribution of product term clusters are automatically considered by the software as it fits functions within a PAL block. The size of a product term cluster has been optimized to provide high utilization of product terms, making complex functions using many product terms possible. Yet when few product terms are used, there will be a minimal number of unused--or wasted--product terms left over. The product term clusters available to each macrocell within a PAL block are shown in Tables 6 and 7. Each product term cluster is associated with a macrocell. The size of a cluster depends on the configuration of the associated macrocell. When the macrocell is used in synchronous mode (Figure 2a), the basic cluster has 4 product terms. When the associated macrocell is used in asynchronous mode (Figure 2b), the cluster has 2 product terms. Note that if the product term cluster is routed to a different macrocell, the allocator configuration is not determined by the mode of the macrocell actually being driven. The configuration is always set by the mode of the macrocell that the cluster will drive if not routed away, regardless of the actual routing. In addition, there is an extra product term that can either join the basic cluster to give an extended cluster, or drive the second input of an exclusive-OR gate in the signal path. If included with the basic cluster, this provides for up to 20 product terms on a synchronous function that uses four extended 5-product-term clusters. A similar asynchronous function can have up to 18 product terms. When the extra product term is used to extend the cluster, the value of the second XOR input can be programmed as a 0 or a 1, giving polarity control. The possible configurations of the logic allocator are shown in Figures 3 and 4. ispMACH 4A Family 7 Table 6. Logic Allocator for All ispMACH 4A Devices (except M4A(3,5)-32/32) Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7, C8 C6, C7, C8, C9 Output Macrocell M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C7, C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15 Table 7. Logic Allocator for M4A(3,5)-32/32 Output Macrocell M0 M1 M2 M3 M4 M5 M6 M7 Available Clusters C0, C1, C2 C0, C1, C2, C3 C1, C2, C3, C4 C2, C3, C4, C5 C3, C4, C5, C6 C4, C5, C6, C7 C5, C6, C7 C6, C7 From n-1 Output Macrocell M8 M9 M10 M11 M12 M13 M14 M15 Available Clusters C8, C9, C10 C8, C9, C10, C11 C9, C10, C11, C12 C10, C11, C12, C13 C11, C12, C13, C14 C12, C13, C14, C15 C13, C14, C15 C14, C15 To n-1 To n-2 Logic Allocator Basic Product Term Cluster n n 0 Default To n+1 From n+1 From n+2 Extra Product Term 0 Default Prog. Polarity To Macrocell n 17466G-005 a. Synchronous Mode From n-1 To n-1 To n-2 Logic Allocator Basic Product Term Cluster n n 0 Default Extra Product Term 0 Default From n+1 From n+2 To n+1 Prog. Polarity b. Asynchronous Mode To Macrocell n 17466G-006 Figure 2. Logic Allocator: Configuration of Cluster "n" Set by Mode of Macrocell "n" 8 ispMACH 4A Family a. Basic cluster with XOR b. Extended cluster, active high c. Extended cluster, active low 0 d. Basic cluster routed away; single-product-term, active high e. Extended cluster routed away 17466G-007 Figure 3. Logic Allocator Configurations: Synchronous Mode a. Basic cluster with XOR b. Extended cluster, active high c. Extended cluster, active low 0 d. Basic cluster routed away; single-product-term, active high e. Extended cluster routed away 17466G-008 Figure 4. Logic Allocator Configurations: Asynchronous Mode Note that the configuration of the logic allocator has absolutely no impact on the speed of the signal. All configurations have the same delay. This means that designers do not have to decide between optimizing resources or speed; both can be optimized. If not used in the cluster, the extra product term can act in conjunction with the basic cluster to provide XOR logic for such functions as data comparison, or it can work with the D-,T-type flipflop to provide for J-K, and S-R register operation. In addition, if the basic cluster is routed to another macrocell, the extra product term is still available for logic. In this case, the first XOR input will be a logic 0. This circuit has the flexibility to route product terms elsewhere without giving up the use of the macrocell. Product term clusters do not "wrap" around a PAL block. This means that the macrocells at the ends of the block have fewer product terms available. ispMACH 4A Family 9 Macrocell The macrocell consists of a storage element, routing resources, a clock multiplexer, and initialization control. The macrocell has two fundamental modes: synchronous and asynchronous (Figure 5). The mode chosen only affects clocking and initialization in the macrocell. Power-Up Reset PAL-Block Initialization Product Terms Common PAL-block resource Individual macrocell resources SWAP From Logic Allocator From PAL-Clock Generator Block CLK0 Block CLK1 Block CLK2 Block CLK3 AP D/T/L AR Q To Output and Input Switch Matrices 17466G-009 a. Synchronous mode Power-Up Reset Individual Initialization Product Term From Logic Allocator From PAL-Block Clock Generator Individual Clock Product Term Block CLK0 Block CLK1 AP AR Q D/T/L To Output and Input Switch Matrices b. Asynchronous mode 17466G-010 Figure 5. Macrocell In either mode, a combinatorial path can be used. For combinatorial logic, the synchronous mode will generally be used, since it provides more product terms in the allocator. 10 ispMACH 4A Family The flip-flop can be configured as a D-type or T-type latch. J-K or S-R registers can be synthesized. The primary flip-flop configurations are shown in Figure 6, although others are possible. Flip-flop functionality is defined in Table 8. Note that a J-K latch is inadvisable as it will cause oscillation if both J and K inputs are HIGH. AP AR D Q AP AR D Q a. D-type with XOR b. D-type with programmable D polarity L AP AR Q AP AR L Q G G c. Latch with XOR d. Latch with programmable D polarity AP AR T Q f. Combinatorial with XOR e. T-type with programmable T polarity g. Combinatorial with programmable polarity 17466G-011 Figure 6. Primary Macrocell Configurations ispMACH 4A Family 11 Table 8. Register/Latch Operation Configuration D-type Register Input(s) D=X D=0 D=1 T=X T=0 T=1 D=X D=0 D=1 CLK/LE 1 0,1, () () () 0, 1, () () () 1(0) 0(1) 0(1) Q+ Q 0 1 Q Q Q Q 0 1 T-type Register D-type Latch Note: 1. Polarity of CLK/LE can be programmed Although the macrocell shows only one input to the register, the XOR gate in the logic allocator allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product terms are divided between J and K (or S and R). When configured as J-K, S-R, or T-type, the extra product term must be used on the XOR gate input for flip-flop emulation. In any register type, the polarity of the inputs can be programmed. The clock input to the flip-flop can select any of the four PAL block clocks in synchronous mode, with the additional choice of either polarity of an individual product term clock in the asynchronous mode. The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous reset and preset are provided, each driven by a product term common to the entire PAL block. Power-Up Reset PAL-Block Initialization Product Terms AP D/T/L AR Q Power-Up Preset PAL-Block Initialization Product Terms AP D/L AR Q a. Power-up reset 17466G-012 b. Power-up preset 17466G-013 Figure 7. Synchronous Mode Initialization Configurations 12 ispMACH 4A Family A reset/preset swapping feature in each macrocell allows for reset and preset to be exchanged, providing flexibility. In asynchronous mode (Figure 8), a single individual product term is provided for initialization. It can be selected to control reset or preset. Power-Up Reset Individual Reset Product Term Individual Preset Product Term Power-Up Preset AP D/L/T AR Q AP D/L/T AR Q a. Reset 17466G-014 b. Preset 17466G-015 Figure 8. Asynchronous Mode Initialization Configurations Note that the reset/preset swapping selection feature effects power-up reset as well. The initialization functionality of the flip-flops is illustrated in Table 9. The macrocell sends its data to the output switch matrix and the input switch matrix. The output switch matrix can route this data to an output if so desired. The input switch matrix can send the signal back to the central switch matrix as feedback. Table 9. Asynchronous Reset/Preset Operation AR 0 0 1 1 Note: 1. Transparent latch is unaffected by AR, AP AP 0 1 0 1 CLK/LE1 X X X X Q+ See Table 8 1 0 0 ispMACH 4A Family 13 Output Switch Matrix The output switch matrix allows macrocells to be connected to any of several I/O cells within a PAL block. This provides high flexibility in determining pinout and allows design changes to occur without effecting pinout. In ispMACH 4A devices with 2:1 Macrocell-I/O cell ratio, each PAL block has twice as many macrocells as I/O cells. The ispMACH 4A output switch matrix allows for half of the macrocells to drive I/O cells within a PAL block, in combinations according to Figure 9. Each I/O cell can choose from eight macrocells; each macrocell has a choice of four I/O cells. The ispMACH 4A devices with 1:1 Macrocell-I/O cell ratio allow each macrocell to drive one of eight I/O cells (Figure 9). M0 M1 M2 M3 M4 M5 macrocells M6 I/O cell MUX M7 M8 M9 M10 M11 M12 M13 M14 M15 Each I/O cell can choose one of 8 macrocells in all ispMACH 4A devices. Each macrocell can drive one of 4 I/O cells in ispMACH 4A devices with 2:1 macrocell-I/O cell ratio. I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 Each macrocell can drive one of 8 I/O cells in ispMACH 4A devices with 1:1 macrocell-I/O cell ratio except M4A(3, 5)-32/32 devices. Each macrocell can drive one of 8 I/O cells in M4A(3, 5)-32/32 devices. Figure 9. ispMACH 4A Output Switch Matrix Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio Macrocell M0, M1 M2, M3 M4, M5 M6, M7 M8, M9 Routable to I/O Cells I/O0, I/O5, I/O6, I/O7 I/O0, I/O1, I/O6, I/O7 I/O0, I/O1, I/O2, I/O7 I/O0, I/O1, I/O2, I/O3 I/O1, I/O2, I/O3, I/O4 14 ispMACH 4A Family Table 10. Output Switch Matrix Combinations for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio Macrocell M10, M11 M12, M13 M14, M15 I/O Cell I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 Routable to I/O Cells I/O2, I/O3, I/O4, I/O5 I/O3, I/O4, I/O5, I/O6 I/O4, I/O5, I/O6, I/O7 Available Macrocells M0, M1, M2, M3, M4, M5, M6, M7 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M0, M1, M10, M11, M12, M13, M14, M15 M0, M1, M2, M3, M12, M13, M14, M15 M0, M1, M2, M3, M4, M5, M14, M15 Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192 Macrocell M0 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 I/O Cell I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 M0 M0 M0 M0 M0 M0 M0 M1 M1 M1 M1 M1 M1 M1 M2 M2 M2 M2 M2 M2 M2 M3 M3 M3 M3 M3 M3 M3 I/O0 I/O0 I/O0 I/O0 I/O0 I/O0 I/O0 I/O0 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O8 I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 I/O1 I/O9 I/O9 I/O9 I/O9 I/O9 I/O9 I/O9 I/O9 I/O2 I/O2 I/O2 I/O2 I/O2 I/O2 I/O2 I/O2 I/O10 I/O10 I/O10 I/O10 I/O10 I/O10 I/O10 I/O10 I/O3 I/O3 I/O3 I/O3 I/O3 I/O3 I/O3 I/O3 I/O11 I/O11 I/O11 I/O11 I/O11 I/O11 I/O11 I/O11 Routable to I/O Cells I/O4 I/O4 I/O4 I/O4 I/O4 I/O4 I/O4 I/O4 I/O12 I/O12 I/O12 I/O12 I/O12 I/O12 I/O12 I/O12 I/O5 I/O5 I/O5 I/O5 I/O5 I/O5 I/O5 I/O5 I/O13 I/O13 I/O13 I/O13 I/O13 I/O13 I/O13 I/O13 I/O6 I/O6 I/O6 I/O6 I/O6 I/O6 I/O6 I/O6 I/O14 I/O14 I/O14 I/O14 I/O14 I/O14 I/O14 I/O14 I/O7 I/O7 I/O7 I/O7 I/O7 I/O7 I/O7 I/O7 I/O15 I/O15 I/O15 I/O15 I/O15 I/O15 I/O15 I/O15 Available Macrocells M4 M4 M4 M4 M4 M4 M4 M5 M5 M5 M5 M5 M5 M5 M6 M6 M6 M6 M6 M6 M6 M7 M7 M7 M7 M7 M7 M7 ispMACH 4A Family 15 Table 11. Output Switch Matrix Combinations for M4A3-256/160 and M4A3-256/192 Macrocell I/O7 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 M0 M8 M8 M8 M8 M8 M8 M8 M8 M1 M9 M9 M9 M9 M9 M9 M9 M9 M2 M10 M10 M10 M10 M10 M10 M10 M10 M3 M11 M11 M11 M11 M11 M11 M11 M11 Routable to I/O Cells M4 M12 M12 M12 M12 M12 M12 M12 M12 M5 M13 M13 M13 M13 M13 M13 M13 M13 M6 M14 M14 M14 M14 M14 M14 M14 M14 M7 M15 M15 M15 M15 M15 M15 M15 M15 Table 12. Output Switch Matrix Combinations for M4A(3,5)-32/32 Macrocell M0, M1, M2, M3, M4, M5, M6, M7 M8, M9, M10, M11, M12, M13, M14, M15 I/O Cell I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 Routable to I/O Cells I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 Available Macrocells M0, M1, M2, M3, M4, M5, M6, M7 M8, M9, M10, M11, M12, M13, M14, M15 Table 13. Output Switch Matrix Combinations for M4A3-64/64 Macrocell MO, M1 M2, M3 M4, M5 M6, M7 M8, M9 M10, M11 M12, M13 M14, M15 I/O Cell I/O0, I/O1 I/O2, I/O3 I/O4, I/O5 I/O6, I/O7 I/O8, I/O9 I/O10, I/O11 I/O12, I/O13 I/O14, I/O15 Routable to I/O Cells I/O0, I/O1, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 I/O0, I/O1, I/O2, I/O3, I/O12, I/O13, I/O14, I/O15 I/O0, I/O1, I/O2,I/O3, I/O4,I/O5, I/O14, I/O15 I/O0, I/O1, I/O2, I/O3, I/O4, I/O5, I/O6, I/O7 I/O2, I/O3, I/O4, I/O5, I/O6, I/O7, I/O8, I/O9 I/O4, I/O5, I/O6, I/O7, I/O8, I/O9, I/O10, I/O11 I/O6, I/O7, I/O8, I/O9, I/O10, I/O11, I/O12, I/O13 I/O8, I/O9, I/O10, I/O11, I/O12, I/O13, I/O14, I/O15 Available Macrocells M0, M1, M2, M3, M4, M5, M6, M7 M2, M3, M4, M5, M6, M7, M8, M9 M4, M5, M6, M7, M8, M9, M10, M11 M6, M7, M8, M9, M10, M11, M12, M13 M8, M9, M10, M11, M12, M13, M14, M15 M0, M1, M10, M11, M12, M13, M14, M15 M0, M1, M2, M3, M12, M13, M14, M15 M0, M1, M2, M3, M4, M5, M14, M15 16 ispMACH 4A Family I/O Cell The I/O cell (Figures 10 and 11) simply consists of a programmable output enable, a feedback path, and flip-flop (except ispMACH 4A devices with 1:1 macrocell-I/O cell ratio). An individual output enable product term is provided for each I/O cell. The feedback signal drives the input switch matrix. Individual Output Enable Product Term From Output Switch Matrix Individual Output Enable Product Term From Output Switch Matrix To Input Switch Matrix Q D/L Block CLK0 Block CLK1 Block CLK2 Block CLK3 Power-up reset 17466G-017 17466G-018 To Input Switch Matrix Figure 10. I/O Cell for ispMACH 4A Devices with 2:1 Macrocell-I/O Cell Ratio Figure 11. I/O Cell for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio The I/O cell (Figure 10) contains a flip-flop, which provides the capability for storing the input in a D-type register or latch. The clock can be any of the PAL block clocks. Both the direct and registered versions of the input are sent to the input switch matrix. This allows for such functions as "time-domain-multiplexed" data comparison, where the first data value is stored, and then the second data value is put on the I/O pin and compared with the previous stored value. Note that the flip-flop used in the ispMACH 4A I/O cell is independent of the flip-flops in the macrocells. It powers up to a logic low. Zero-Hold-Time Input Register The ispMACH 4A devices have a zero-hold-time (ZHT) fuse which controls the time delay associated with loading data into all I/O cell registers and latches. When programmed, the ZHT fuse increases the data path setup delays to input storage elements, matching equivalent delays in the clock path. When the fuse is erased, the setup time to the input storage element is minimized. This feature facilitates doing worst-case designs for which data is loaded from sources which have low (or zero) minimum output propagation delays from clock edges. ispMACH 4A Family 17 Input Switch Matrix The input switch matrix (Figures 12 and 13) optimizes routing of inputs to the central switch matrix. Without the input switch matrix, each input and feedback signal has only one way to enter the central switch matrix. The input switch matrix provides additional ways for these signals to enter the central switch matrix. From Input Cell From Macrocell 1 From Macrocell 2 Direct Registered/Latched To Central Switch Matrix 17466G-002 To Central Switch Matrix Figure 12. ispMACH 4A with 2:1 Macrocell-I/O Cell Ratio - Input Switch Matrix Figure 13. ispMACH 4A with 1:1 Macrocell-I/O Cell Ratio - Input Switch Matrix 18 ispMACH 4A Family From Macrocell 17466G-003 From I/O Pin PAL Block Clock Generation Each ispMACH 4A device has four clock pins that can also be used as inputs. These pins drive a clock generator in each PAL block (Figure 14). The clock generator provides four clock signals that can be used anywhere in the PAL block. These four PAL block clock signals can consist of a large number of combinations of the true and complement edges of the global clock signals. Table 14 lists the possible combinations. GCLK0 Block CLK0 (GCLK0 or GCLK1) GCLK1 Block CLK1 (GCLK1 or GCLK0) Block CLK2 (GCLK2 or GCLK3) Block CLK3 (GCLK3 or GCLK2) 17466G-004 GCLK2 GCLK3 Figure 14. PAL Block Clock Generator 1 1. M4A(3,5)-32/32 and M4A(3,5)-64/32 have only two clock pins, GCLK0 and GCLK1. GCLK2 is tied to GCLK0, and GCLK3 is tied to GCLK1. Table 14. PAL Block Clock Combinations1 Block CLK0 GCLK0 GCLK1 GCLK0 GCLK1 X X X X Block CLK1 GCLK1 GCLK1 GCLK0 GCLK0 X X X X Block CLK2 X X X X GCLK2 (GCLK0) GCLK3 (GCLK1) GCLK2 (GCLK0) GCLK3 (GCLK1) Block CLK3 X X X X GCLK3 (GCLK1) GCLK3 (GCLK1) GCLK2 (GCLK0) GCLK2 (GCLK0) Note: 1. Values in parentheses are for the M4A(3,5)-32/32 and M4A(3,5)-64/32. This feature provides high flexibility for partitioning state machines and dual-phase clocks. It also allows latches to be driven with either polarity of latch enable, and in a master-slave configuration. ispMACH 4A Family 19 ispMACH 4A TIMING MODEL The primary focus of the ispMACH 4A timing model is to accurately represent the timing in a ispMACH 4A device, and at the same time, be easy to understand. This model accurately describes all combinatorial and registered paths through the device, making a distinction between internal feedback and external feedback. A signal uses internal feedback when it is fed back into the switch matrix or block without having to go through the output buffer. The input register specifications are also reported as internal feedback. When a signal is fed back into the switch matrix after having gone through the output buffer, it is using external feedback. The parameter, tBUF, is defined as the time it takes to go from feedback through the output buffer to the I/O pad. If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is followed by an "i". By adding tBUF to this internal parameter, the external parameter is derived. For example, tPD = tPDi + tBUF. A diagram representing the modularized ispMACH 4A timing model is shown in Figure 15. Refer to the application note entitled MACH 4 Timing and High Speed Design for a more detailed discussion about the timing parameters. (External Feedback) (Internal Feedback) COMB/DFF/TFF/ LATCH/SR*/JK* IN Central Switch Matrix *emulated tSLW tBUF OUT tPL INPUT REG/ INPUT LATCH tSIRS tHIRS tSIL tHIL tSIRZ tHIRZ tSILZ tHILZ BLK CLK tPDILi tICOSi tIGOSi tPDILZi Q tSS(T) tSA(T) tH(S/A) tS(S/A)L tH(S/A)L tSRR tPDi Q tPDLi tCO(S/A)i tGO(S/A)i tSRi S/R tEA tER 17466G-025 Figure 15. ispMACH 4A Timing Model SPEEDLOCKING FOR GUARANTEED FIXED TIMING The ispMACH 4A architecture allows allocation of up to 20 product terms to an individual macrocell with the assistance of an XOR gate without incurring additional timing delays. The design of the switch matrix and PAL blocks guarantee a fixed pin-to-pin delay that is independent of the logic required by the design. Other competitive CPLDs incur serious timing delays as product terms expand beyond their typical 4 or 5 product term limits. Speed and SpeedLocking combine to give designs easy access to the performance required in today's designs. 20 ispMACH 4A Family IEEE 1149.1-COMPLIANT BOUNDARY SCAN TESTABILITY All ispMACH 4A devices have boundary scan cells and are compliant to the IEEE 1149.1 standard. This allows functional testing of the circuit board on which the device is mounted through a serial scan path that can access all critical logic nodes. Internal registers are linked internally, allowing test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and shifted out for verification. In addition, these devices can be linked into a boardlevel serial scan path for more complete board-level testing. IEEE 1149.1-COMPLIANT IN-SYSTEM PROGRAMMING Programming devices in-system provides a number of significant benefits including: rapid prototyping, lower inventory levels, higher quality, and the ability to make in-field modifications. All ispMACH 4A devices provide In-System Programming (ISP) capability through their Boundary ScanTest Access Ports. This capability has been implemented in a manner that ensures that the port remains compliant to the IEEE 1149.1 standard. By using IEEE 1149.1 as the communication interface through which ISP is achieved, customers get the benefit of a standard, well-defined interface. ispMACH 4A devices can be programmed across the commercial temperature and voltage range. The PC-based LatticePRO software facilitates in-system programming of ispMACH 4A devices. LatticePRO takes the JEDEC file output produced by the design implementation software, along with information about the JTAG chain, and creates a set of vectors that are used to drive the JTAG chain. LatticePRO software can use these vectors to drive a JTAG chain via the parallel port of a PC. Alternatively, LatticePRO software can output files in formats understood by common automated test equipment. This equpment can then be used to program ispMACH 4A devices during the testing of a circuit board. PCI COMPLIANT ispMACH 4A devices in the -5/-55/-6/-65/-7/-10/-12 speed grades are compliant with the PCI Local Bus Specification version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to clamp the inputs as they rise above VCC because of their 5-V input tolerant feature. SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS Both the 3.3-V and 5-V VCC ispMACH 4A devices are safe for mixed supply voltage system designs. The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they accept inputs from other 3.3-V devices. The 3.3-V device will accept inputs up to 5.5 V. Both the 5-V and 3.3-V versions have the same high-speed performance and provide easy-touse mixed-voltage design capability. PULL UP OR BUS-FRIENDLY INPUTS AND I/Os All ispMACH 4A devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating two inverters in series which loop back to the input. This double inversion weakly holds the input at its last driven logic state. While it is good design practice to tie unused pins to a known state, the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level "1." For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. ispMACH 4A Family 21 All ispMACH 4A devices have a programmable bit that configures all inputs and I/Os with either pull-up or Bus-Friendly characteristics. If the device is configured in pull-up mode, all inputs and I/O pins are weakly pulled up. For the circuit diagram, please refer to the document entitled MACH Endurance Characteristics on the Lattice Data Book CD-ROM or Lattice web site. POWER MANAGEMENT Each individual PAL block in ispMACH 4A devices features a programmable low-power mode, which results in power savings of up to 50%. The signal speed paths in the low-power PAL block will be slower than those in the non-low-power PAL block. This feature allows speed critical paths to run at maximum frequency while the rest of the signal paths operate in the low-power mode. PROGRAMMABLE SLEW RATE Each ispMACH 4A device I/O has an individually programmable output slew rate control bit. Each output can be individually configured for the higher speed transition (3 V/ns) or for the lower noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slowslew rate will introduce fewer reflections, less noise, and keep ground bounce to a minimum. For designs with short traces or well terminated lines, the fast slew rate can be used to achieve the highest speed. The slew rate is adjusted independent of power. POWER-UP RESET/SET All flip-flops power up to a known state for predictable system initialization. If a macrocell is configured to SET on a signal from the control generator, then that macrocell will be SET during device power-up. If a macrocell is configured to RESET on a signal from the control generator or is not configured for set/reset, then that macrocell will RESET on power-up. To guarantee initialization values, the VCC rise must be monotonic, and the clock must be inactive until the reset delay time has elapsed. SECURITY BIT A programmable security bit is provided on the ispMACH 4A devices as a deterrent to unauthorized copying of the array configuration patterns. Once programmed, this bit defeats readback of the programmed pattern by a device programmer, securing proprietary designs from competitors. Programming and verification are also defeated by the security bit. The bit can only be reset by erasing the entire device. HOT SOCKETING ispMACH 4A devices are well-suited for those applications that require hot socketing capability. Hot socketing a device requires that the device, when powered down, can tolerate active signals on the I/Os and inputs without being damaged. Additionally, it requires that the effects of the powered-down MACH devices be minimal on active signals. 22 ispMACH 4A Family CLK0 CLK1 CLK2 CLK3 A CLOCK GENERATOR 4 0 M4A(3, 5)-64/32 M4A3-64/64 M4A(3, 5)-96/48 M4A(3, 5)-128/64 A B 16 17 M4(3, 5)-192/96 M4(3, 5)-256/128 17 17 M4A3-384 M4A3-512 18 18 C0 M0 M0 M1 MACROCELL M1 O0 I/O CELL MACROCELL I/O0 C1 C2 M2 M2 M3 MACROCELL M3 O1 MACROCELL I/O CELL I/O1 C3 C4 M4 M4 M5 MACROCELL M5 O2 MACROCELL I/O CELL I/O2 C5 C6 CENTRAL SWITCH MATRIX LOGIC ALLOCATOR M6 OUTPUT SWITCH MATRIX M6 M7 MACROCELL M7 MACROCELL O3 I/O CELL I/O3 C7 C8 M8 M8 M9 MACROCELL M9 MACROCELL O4 C9 I/O CELL I/O4 C10 M10 M10 M11 MACROCELL M11 O5 MACROCELL I/O CELL I/O5 C11 C12 M12 M12 M13 MACROCELL M13 O6 I/O CELL MACROCELL I/O6 C13 C14 M14 M14 M15 MACROCELL M15 MACROCELL O7 I/O CELL I/O7 C15 89 B 16 24 INPUT SWITCH MATRIX 16 Figure 16. PAL Block for ispMACH 4A with 2:1 Macrocell - I/O Cell Ratio ispMACH 4A Family 23 CLK0 CLK1 CLK2 CLK3 M4A3-64/64 A B 16 17 M4A3-256/160 M4A3-256/192 18 18 A CLOCK GENERATOR 4 0 M0 C0 M0 M1 C1 MACROCELL M1 MACROCELL O1 O0 I/O CELL I/O CELL I/O0 I/O1 C2 M2 M2 M3 MACROCELL M3 MACROCELL O2 O3 I/O CELL I/O CELL I/O2 I/O3 C3 C4 M4 M4 M5 MACROCELL M5 MACROCELL O4 I/O CELL I/O CELL I/O4 I/O5 C5 O5 CENTRAL SWITCH MATRIX LOGIC ALLOCATOR M7 M7 MACROCELL OUTPUT SWITCH MATRIX C6 M6 M6 MACROCELL O6 I/O CELL I/O CELL I/O6 I/O7 C7 O7 C8 M8 M8 M9 MACROCELL M9 MACROCELL O8 I/O CELL I/O CELL I/O8 I/O9 C9 O9 C10 M10 M10 MACROCELL M11 MACROCELL O10 I/O CELL I/O CELL I/O10 I/O11 C11 M11 O11 C12 M12 M12 MACROCELL M13 MACROCELL O12 I/O CELL I/O CELL I/O12 I/O13 C13 M13 O13 C14 M14 M14 MACROCELL M15 MACROCELL O14 I/O CELL I/O CELL I/O14 C15 M15 97 B 16 32 INPUT SWITCH MATRIX I/O15 O15 16 17466H-41 Figure 17. PAL Block for ispMACH 4A Devices with 1:1 Macrocell-I/O Cell Ratio (except M4A (3,5)-32/32) 24 ispMACH 4A Family CLK0/I0 16 CLK0/I1 CLOCK GENERATOR 2 0 M0 C0 M0 M1 C1 MACROCELL M1 MACROCELL O1 O0 I/O CELL I/O CELL I/O0 I/O1 C2 M2 M3 OUTPUT SWITCH MATRIX M2 M3 MACROCELL MACROCELL O2 O3 I/O CELL I/O CELL I/O2 I/O3 C3 C4 M4 M4 M5 MACROCELL M5 MACROCELL O4 I/O CELL I/O CELL I/O4 I/O5 C5 O5 CENTRAL SWITCH MATRIX C6 LOGIC ALLOCATOR M6 M6 M7 MACROCELL M7 MACROCELL O7 O6 I/O CELL I/O CELL I/O6 I/O7 C7 C8 M8 M8 M9 MACROCELL M9 MACROCELL O8 I/O CELL I/O CELL I/O8 I/O9 C9 O9 C10 M10 M11 OUTPUT SWITCH MATRIX M10 MACROCELL MACROCELL O10 I/O CELL I/O CELL I/O10 I/O11 C11 M11 O11 C12 M12 M12 MACROCELL M13 MACROCELL O12 I/O CELL I/O CELL I/O12 I/O13 C13 M13 O13 C14 M14 M14 MACROCELL M15 MACROCELL O14 I/O CELL I/O CELL I/O14 C15 M15 97 17 16 32 INPUT SWITCH MATRIX I/O15 O15 16 Figure 18. PAL Block for M4A (3,5)-32/32 17466H-042 ispMACH 4A Family 25 BLOCK DIAGRAM - M4A(3,5)-32/32 Block A I/O8-I/O15 I/O0-I/O7 8 I/O Cells Clock Generator 8 Output Switch Matrix 8 Macrocells OE 8 Input Switch Matrix 2 OE 8 4 8 I/O Cells 8 Output Switch Matrix 8 8 Macrocells 8 Input Switch Matrix 16 16 Input Switch Matrix 8 Macrocells 8 Clock Generator 4 8 4 8 8 8 Output Switch Matrix 8 I/O Cells 8 I/O24-I/O31 8 8 8 4 8 66 X 98 AND Logic Array and Logic Allocator 33 CLK0/I0, CLK1/I1 16 2 2 16 Input Switch Matrix Central Switch Matrix 33 66 X 98 AND Logic Array and Logic Allocator OE OE 8 Macrocells 8 8 8 Output Switch Matrix 8 I/O Cells 8 2 I/O16-I/O23 Block B 17466H-019 26 ispMACH 4A Family BLOCK DIAGRAM - M4A(3,5)-64/32 Block A I/O0-I/O7 Block D I/O24-I/O31 8 I/O Cells Clock Generator Clock Generator 4 8 4 8 Output Switch Matrix 16 Macrocells OE OE 16 Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 2 4 8 4 8 I/O Cells 8 Output Switch Matrix 16 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator Input Switch Matrix 24 24 Input Switch Matrix 16 16 8 4 Output Switch Matrix 8 I/O Cells 8 16 16 16 16 2 CLK0/I0, CLK1/I1 33 24 33 2 2 33 Central Switch Matrix 24 Input Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator OE 16 Macrocells 16 16 8 4 Output Switch Matrix 8 I/O Cells 8 16 Clock Generator 4 2 OE Clock Generator 4 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 2 I/O8-I/O15 I/O16-I/O23 Block B Block C 17466H-020 ispMACH 4A Family 27 BLOCK DIAGRAM - M4A3-64/64 Block A Block D 16 I/O Cells Clock Generator Clock Generator 16 16 4 Output Switch Matrix 16 Macrocells OE OE 16 66 X 90 AND Logic Array and Logic Allocator 4 16 I/O Cells 16 Output Switch Matrix 16 16 Macrocells 16 66 X 90 AND Logic Array and Logic Allocator 16 16 16 4 16 4 CLK0/I0, CLK1/I1 CLK2/I3, CLK3/I4 33 33 4 4 33 Central Switch Matrix 33 66 X 90 AND Logic Array and Logic Allocator OE 16 Macrocells 16 16 Output Switch Matrix 16 I/O Cells 16 16 Clock Generator 4 16 16 16 Output Switch Matrix 16 I/O Cells 16 16 2 4 OE Clock Generator 4 16 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 4 Block B Block C 17466H-020A 28 ispMACH 4A Family Block C I/O16-I/O23 I/O8-I/O15 I/O0-I/O7 Block B Block A 8 I/O Cells 4 8 16 16 16 Macrocells OE OE 16 Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 4 24 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 4 16 16 4 16 16 16 4 Macrocells OE 16 Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 4 24 33 16 Output Switch Matrix 8 8 Output Switch Matrix Output Switch Matrix Clock Generator 8 4 Clock Generator 8 4 8 I/O Cells I/O Cells 8 8 BLOCK DIAGRAM - M4A(3,5)-96/48 33 33 24 Input Switch Matrix 4 Clock Generator 4 33 24 33 24 Central Switch Matrix 33 24 I2, I3, I6, I7 CLK0/I0, CLK1/I1, CLK2/I4, CLK3/I5 ispMACH 4A Family Input Switch Matrix Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 4 OE OE 16 16 Macrocells 16 16 8 Output Switch Matrix 8 I/O Cells 8 4 4 16 8 4 16 16 Output Switch Matrix 8 I/O Cells 8 16 4 8 4 Macrocells 4 66 X 90 AND Logic Array and Logic Allocator 4 OE 16 16 Clock Generator Clock Generator 8 8 I/O24-I/O31 I/O32-I/O39 4 4 Input Switch Matrix 4 66 X 90 AND Logic Array and Logic Allocator Macrocells 16 16 Output Switch Matrix Clock Generator I/O Cells 17466G-021 I/O40-I/O47 29 Block D Block E Block F Block D I/O24-I/031 I/O16-I/O23 I/O8-I/O15 I/O0-I/O7 Block C Block B Block A 8 8 I/O Cells 4 8 4 16 Macrocells OE 16 Output Switch Matrix 8 I/O Cells 8 4 8 16 16 Macrocells OE OE 16 4 4 Input Switch Matrix Input Switch Matrix 66 X 90 AND Logic Array and Logic Allocator 24 33 24 33 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 4 16 16 16 4 16 Output Switch Matrix 8 Output Switch Matrix 4 Output Switch Matrix 16 16 16 Macrocells 16 Input Switch Matrix 4 8 8 I/O Cells I/O Cells 8 8 4 Input Switch Matrix 4 BLOCK DIAGRAM - M4A(3,5)-128/64 Clock Generator Clock Generator Clock Generator 16 16 66 X 90 AND Logic Array and Logic Allocator 33 24 33 24 Clock Generator 8 4 OE 66 X 90 AND Logic Array and Logic Allocator I2, I5 4 33 24 33 24 33 Central Switch Matrix 24 33 24 CLK0/I0, CLK1/I1, CLK2/I3, CLK3/I4 ispMACH 4A Family Input Switch Matrix Input Switch Matrix Input Switch Matrix 4 OE OE 66 X 90 AND Logic Array and Logic Allocator 4 16 Macrocells 16 16 Output Switch Matrix 8 8 I/O Cells 8 I/O Cells 8 4 16 8 Output Switch Matrix 16 4 16 16 4 8 4 66 X 90 AND Logic Array and Logic Allocator 16 Macrocells 16 16 Output Switch Matrix 8 I/O Cells 8 16 4 16 Macrocells Clock Generator Clock Generator I/O32-I/O39 Block E I/O40-I/O47 Block F I/O48-I/O55 Block G 4 2 Input Switch Matrix 4 66 X 90 AND Logic Array and Logic Allocator 66 X 90 AND Logic Array and Logic Allocator OE 16 Macrocells 4 8 4 4 Clock Generator Clock Generator 4 OE 16 16 Output Switch Matrix 8 I/O Cells 8 16 8 I/O56-I/O63 Block H 17466H-022 30 BLOCK DIAGRAM - M4A(3,5)-192/96 Block B I/O8-I/O15 Block A I/O0-I/O7 CLK0-CLK3 Block L I/O88-I/O95 Block K I/O80-I/O87 8 8 4 4 8 8 I/O Cells Clock Generator 8 4 8 4 I/O Cells 8 I/O Cells Clock Generator Clock Generator 4 8 4 4 8 4 8 I/O Cells Clock Generator 4 8 4 8 Output Switch Matrix 16 16 16 16 Output Switch Matrix 16 Output Switch Matrix 16 16 Output Switch Matrix 16 16 Macrocells OE 16 16 Macrocells OE OE 16 Macrocells 16 16 OE Macrocells 16 16 Input Switch Matrix Input Switch Matrix 68 X 90 AND Logic Array and Logic Allocator 34 4 68 X 90 AND Logic Array and Logic Allocator 34 4 4 68 X 90 AND Logic Array and Logic Allocator 34 Input Switch Matrix 4 68 X 90 AND Logic Array and Logic Allocator 34 24 24 24 24 Input Switch Matrix Block C I/O16-I/O23 Block D I/O24-I/O31 8 8 8 8 I/O72-I/O79 Block J I/O64-I/O71 Block I I/O Cells Clock Generator 8 4 8 4 I/O Cells I/O Cells I/O Cells Clock Generator 4 8 4 8 Central Switch Matrix 8 Clock Generator Clock Generator 4 8 4 4 8 4 8 Output Switch Matrix 16 16 16 Output Switch Matrix 16 16 16 Output Switch Matrix 16 16 Output Switch Matrix 16 16 Macrocells OE 16 Macrocells OE 16 Macrocells OE 16 16 OE Macrocells 16 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 68 X 90 AND Logic Array and Logic Allocator 34 4 68 X 90 AND Logic Array and Logic Allocator 34 4 4 68 X 90 AND Logic Array and Logic Allocator 34 4 68 X 90 AND Logic Array and Logic Allocator 34 24 24 24 24 24 34 24 34 34 24 34 24 Input Switch Matrix Input Switch Matrix Input Switch Matrix 68 X 90 AND Logic Array and Logic Allocator OE 16 4 68 X 90 AND Logic Array and Logic Allocator OE 16 4 4 OE 68 X 90 AND Logic Array and Logic Allocator 16 4 OE 68 X 90 AND Logic Array and Logic Allocator 16 16 Macrocells Clock Generator 16 4 8 4 16 Macrocells 16 Macrocells Clock Generator Clock Generator 4 8 4 4 8 4 16 16 Macrocells Clock Generator 4 8 4 16 16 16 Output Switch Matrix 8 16 Output Switch Matrix 8 Output Switch Matrix 8 16 Output Switch Matrix 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 16 I/O32-I/O39 Block E I/O40-I/O47 Block F I0-I15 I/O48-I/O55 Block G I/O56-I/O63 Block H Input Switch Matrix 16 Input Switch Matrix 17466G-067 ispMACH 4A Family 31 BLOCK DIAGRAM - M4A(3,5)-256/128 Block B I/O8-I/O15 Block A I/O0-I/O7 CLK0-CLK3 Block P I/O120-I/O127 Block O I/O112-I/O119 8 8 4 4 8 8 I/O Cells Clock Generator 8 4 8 4 I/O Cells 8 I/O Cells Clock Generator Clock Generator 4 8 4 4 8 4 8 I/O Cells Clock Generator 4 8 4 8 Output Switch Matrix 16 16 16 16 Output Switch Matrix 16 Output Switch Matrix 16 16 Output Switch Matrix 16 16 Macrocells OE 16 16 Macrocells OE OE 16 Macrocells 16 16 OE Macrocells 16 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 68 X 90 AND Logic Array and Logic Allocator 34 4 68 X 90 AND Logic Array and Logic Allocator 34 4 4 68 X 90 AND Logic Array and Logic Allocator 34 4 68 X 90 AND Logic Array and Logic Allocator 34 24 24 24 24 24 34 24 34 34 24 34 24 Input Switch Matrix Input Switch Matrix Input Switch Matrix 68 X 90 AND Logic Array and Logic Allocator OE 16 4 68 X 90 AND Logic Array and Logic Allocator OE 16 4 4 OE 68 X 90 AND Logic Array and Logic Allocator 16 4 OE 68 X 90 AND Logic Array and Logic Allocator 16 16 Macrocells Clock Generator 16 4 8 4 16 Macrocells 16 Macrocells Clock Generator Clock Generator 4 8 4 4 8 4 16 16 Macrocells Clock Generator 4 8 4 16 16 16 Output Switch Matrix 8 16 Output Switch Matrix 8 Output Switch Matrix 8 16 Output Switch Matrix 8 I/O Cells 8 I/O Cells I/O Cells I/O Cells 8 8 Central Switch Matrix Block C I/O16-I/O23 Block D I/O24-I/O31 Block E I/O32-I/O39 Block F I/O40-I/O47 8 8 8 Input Switch Matrix 16 Input Switch Matrix I/O104-I/O111 Block N I/O96-I/O103 Block M I/O88-I/O95 Block L I/O80-I/O87 Block K 8 8 I/O Cells Clock Generator 8 4 8 4 I/O Cells Clock Generator 8 I/O Cells Clock Generator 4 8 4 4 8 4 8 I/O Cells Clock Generator 4 8 4 8 Output Switch Matrix 16 16 16 Output Switch Matrix 16 16 16 Output Switch Matrix 16 16 Output Switch Matrix 16 16 Macrocells OE 16 Macrocells OE OE 16 Macrocells 16 16 OE Macrocells 16 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 68 X 90 AND Logic Array and Logic Allocator 34 4 68 X 90 AND Logic Array and Logic Allocator 34 4 4 68 X 90 AND Logic Array and Logic Allocator 34 4 68 X 90 AND Logic Array and Logic Allocator 34 24 24 24 24 24 34 24 34 34 24 34 24 Input Switch Matrix Input Switch Matrix Input Switch Matrix 68 X 90 AND Logic Array and Logic Allocator OE 16 4 68 X 90 AND Logic Array and Logic Allocator OE 16 4 4 OE 68 X 90 AND Logic Array and Logic Allocator 16 4 OE 68 X 90 AND Logic Array and Logic Allocator 16 16 Macrocells Clock Generator 16 4 8 4 16 Macrocells 16 Macrocells Clock Generator Clock Generator 4 8 4 4 8 4 16 16 Macrocells Clock Generator 4 8 4 16 16 16 Output Switch Matrix 8 16 Output Switch Matrix 8 Output Switch Matrix 8 16 Output Switch Matrix 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 14 Input Switch Matrix 16 Input Switch Matrix I/O48-I/O55 Block G I/O56-I/O63 Block H I0-I13 I/O64-I/O71 Block I I/O72-I/O79 Block J 17466G-024 32 ispMACH 4A Family BLOCK DIAGRAM - M4A3-256/160, M4A3-256/192 Block B Block A CLK0-CLK3 Block P Block O 4 16 16 16 16 4 I/O Cells I/O Cells I/O Cells I/O Cells Clock Generator 16 4 16 4 16 Clock Generator Clock Generator 4 16 4 4 16 4 16 Clock Generator 4 16 4 16 Output Switch Matrix 16 16 16 16 Output Switch Matrix 16 Output Switch Matrix 16 16 Output Switch Matrix 16 16 Macrocells 16 Macrocells Macrocells 16 Macrocells 16 OE OE OE 16 16 16 OE 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 98 AND Logic Array and Logic Allocator 36 4 72 X 98 AND Logic Array and Logic Allocator 36 4 4 72 X 98 AND Logic Array and Logic Allocator 36 4 72 X 98 AND Logic Array and Logic Allocator 36 32 32 32 32 32 36 32 36 36 32 36 32 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 98 AND Logic Array and Logic Allocator 4 72 X 98 AND Logic Array and Logic Allocator 4 4 72 X 98 AND Logic Array and Logic Allocator 4 72 X 98 AND Logic Array and Logic Allocator OE OE OE 16 16 16 OE 16 16 Macrocells 16 Macrocells 16 Macrocells 16 Macrocells 16 Clock Generator 16 16 Clock Generator Clock Generator 4 16 4 4 16 4 4 16 4 16 Clock Generator 4 16 4 16 Output Switch Matrix 16 16 Output Switch Matrix 16 Output Switch Matrix 16 16 Output Switch Matrix 16 I/O Cells 16 I/O Cells I/O Cells I/O Cells 16 16 Central Switch Matrix Block C Block D Block E Block F 16 16 16 Input Switch Matrix 16 Input Switch Matrix Block Block Block Block 16 N M L K 16 I/O Cells I/O Cells I/O Cells I/O Cells Clock Generator Clock Generator 16 4 16 4 16 Clock Generator 4 16 4 4 16 4 16 Clock Generator 4 16 4 16 Output Switch Matrix 16 16 16 Output Switch Matrix 16 16 16 Output Switch Matrix 16 16 Output Switch Matrix 16 16 Macrocells Macrocells Macrocells 16 Macrocells 16 OE OE OE 16 16 16 OE 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 98 AND Logic Array and Logic Allocator 36 4 72 X 98 AND Logic Array and Logic Allocator 36 4 4 72 X 98 AND Logic Array and Logic Allocator 36 4 72 X 98 AND Logic Array and Logic Allocator 36 32 32 32 32 32 36 32 36 36 32 36 32 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 98 AND Logic Array and Logic Allocator 4 72 X 98 AND Logic Array and Logic Allocator 4 4 72 X 98 AND Logic Array and Logic Allocator 4 72 X 98 AND Logic Array and Logic Allocator OE OE OE 16 16 16 OE 16 16 Macrocells 16 Macrocells 16 Macrocells 16 Macrocells 16 Clock Generator 16 16 Clock Generator Clock Generator 4 16 4 4 16 4 4 16 4 16 Clock Generator 4 16 4 16 Output Switch Matrix 16 16 Output Switch Matrix 16 Output Switch Matrix 16 16 Output Switch Matrix 16 I/O Cells 16 I/O Cells 16 I/O Cells 16 I/O Cells 16 Block G Block H Block I Block J ispMACH 4A Family Input Switch Matrix 16 Input Switch Matrix 17466G-050 33 BLOCK DIAGRAM - M4A3-384/160, M4A3-384/192 CLK0-CLK3 Block B Block A 4 Block HX Block GX Detail A 8 8 4 4 8 8 I/O Cells Clock Generator 8 4 8 4 I/O Cells 8 I/O Cells Clock Generator Clock Generator 4 8 4 4 8 4 8 I/O Cells Clock Generator 4 8 4 8 16 Output Switch Matrix 16 16 Output Switch Matrix 16 Output Switch Matrix 16 16 Output Switch Matrix 16 16 16 Macrocells OE 16 16 Macrocells OE OE 16 Macrocells 16 16 OE Macrocells 16 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator 36 4 72 X 90 AND Logic Array and Logic Allocator 36 4 4 72 X 90 AND Logic Array and Logic Allocator 36 4 72 X 90 AND Logic Array and Logic Allocator 36 24 24 24 24 24 36 24 36 36 24 36 24 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator OE 16 4 72 X 90 AND Logic Array and Logic Allocator OE 16 4 4 72 X 90 AND Logic Array and Logic Allocator OE 16 4 OE 72 X 90 AND Logic Array and Logic Allocator 16 Central Switch Matrix 16 Macrocells Clock Generator 16 4 8 4 16 Macrocells 16 Macrocells Clock Generator 4 8 4 16 16 Macrocells Clock Generator 4 8 4 16 16 4 8 4 16 Output Switch Matrix 8 16 Clock Generator Output Switch Matrix 8 Output Switch Matrix 8 16 Output Switch Matrix 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 Block C Block F Block D Block E Block EX Block DX Repeat Detail A Block G Block J 8 Block H Block I 8 8 Block AX Block P 8 I/O Cells Clock Generator 8 4 8 4 I/O Cells 8 I/O Cells Clock Generator Clock Generator 4 8 4 4 8 4 8 I/O Cells Clock Generator 4 8 4 8 16 Output Switch Matrix 16 16 Output Switch Matrix 16 Output Switch Matrix 16 16 Output Switch Matrix 16 16 Macrocells OE 16 16 Macrocells OE OE 16 Macrocells 16 16 OE Macrocells 16 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator 36 4 72 X 90 AND Logic Array and Logic Allocator 36 4 4 72 X 90 AND Logic Array and Logic Allocator 36 4 72 X 90 AND Logic Array and Logic Allocator 36 24 24 24 24 24 36 24 36 36 24 36 24 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator OE 16 4 72 X 90 AND Logic Array and Logic Allocator OE 16 4 4 OE 72 X 90 AND Logic Array and Logic Allocator 16 4 OE 72 X 90 AND Logic Array and Logic Allocator 16 16 Macrocells Clock Generator 16 4 8 4 16 Macrocells 16 Macrocells Clock Generator Clock Generator 4 8 4 4 8 4 16 16 Macrocells Clock Generator 4 8 4 16 16 16 Output Switch Matrix 8 16 Output Switch Matrix 8 Output Switch Matrix 8 16 Output Switch Matrix 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 Block K Block L Block M Block N Input Switch Matrix 16 Input Switch Matrix Input Switch Matrix 16 Input Switch Matrix Block FX Block CX Block BX Block O 16 17466G-067 34 ispMACH 4A Family BLOCK DIAGRAM - M4A3-512/160, M4A3-512/192, M4A3-512/256 CLK0-CLK3 Block B Block A 4 Block PX Block OX Detail A 8 8 4 4 8 8 I/O Cells Clock Generator 8 4 8 4 I/O Cells 8 I/O Cells Clock Generator Clock Generator 4 8 4 4 8 4 8 I/O Cells Clock Generator 4 8 4 8 16 Output Switch Matrix 16 16 Output Switch Matrix 16 Output Switch Matrix 16 16 Output Switch Matrix 16 16 16 Macrocells OE 16 16 Macrocells OE OE 16 Macrocells 16 16 OE Macrocells 16 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator 36 4 72 X 90 AND Logic Array and Logic Allocator 36 4 4 72 X 90 AND Logic Array and Logic Allocator 36 4 72 X 90 AND Logic Array and Logic Allocator 36 24 24 24 24 24 36 24 36 36 24 36 24 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator OE 16 4 72 X 90 AND Logic Array and Logic Allocator OE 16 4 4 72 X 90 AND Logic Array and Logic Allocator OE 16 4 OE 72 X 90 AND Logic Array and Logic Allocator 16 Central Switch Matrix 16 Macrocells Clock Generator 16 4 8 4 16 Macrocells 16 Macrocells Clock Generator 4 8 4 16 16 Macrocells Clock Generator 4 8 4 16 16 4 8 4 16 Output Switch Matrix 8 16 Clock Generator Output Switch Matrix 8 Output Switch Matrix 8 16 Output Switch Matrix 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 Block C Block F Block D Block E Block MX Block LX Repeat Detail A Block G Block J Block H Block I Block IX Block HX Block JX Block GX Repeat Detail A Block K Block N 8 Block L Block M 8 8 Block EX Block DX 8 I/O Cells Clock Generator 8 4 8 4 I/O Cells 8 I/O Cells Clock Generator Clock Generator 4 8 4 4 8 4 8 I/O Cells Clock Generator 4 8 4 8 16 Output Switch Matrix 16 16 Output Switch Matrix 16 Output Switch Matrix 16 16 Output Switch Matrix 16 16 Macrocells OE 16 16 Macrocells OE OE 16 Macrocells 16 16 OE Macrocells 16 16 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator 36 4 72 X 90 AND Logic Array and Logic Allocator 36 4 4 72 X 90 AND Logic Array and Logic Allocator 36 4 72 X 90 AND Logic Array and Logic Allocator 36 24 24 24 24 24 36 24 36 36 24 36 24 Input Switch Matrix Input Switch Matrix Input Switch Matrix 72 X 90 AND Logic Array and Logic Allocator OE 16 4 72 X 90 AND Logic Array and Logic Allocator OE 16 4 4 OE 72 X 90 AND Logic Array and Logic Allocator 16 4 OE 72 X 90 AND Logic Array and Logic Allocator 16 16 Macrocells Clock Generator 16 4 8 4 16 Macrocells 16 Macrocells Clock Generator Clock Generator 4 8 4 4 8 4 16 16 Macrocells Clock Generator 4 8 4 16 16 16 Output Switch Matrix 8 16 Output Switch Matrix 8 Output Switch Matrix 8 16 Output Switch Matrix 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 I/O Cells 8 Block O Block P Block AX Block BX Input Switch Matrix 16 Input Switch Matrix Input Switch Matrix 16 Input Switch Matrix Block NX Block KX Block FX Block CX 16 17466G-068 ispMACH 4A Family 35 ABSOLUTE MAXIMUM RATINGS M4A5 Storage Temperature . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . .-55C to +100C Device Junction Temperature . . . . . . . . . . . . . . . +130C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +7.0 V DC Input Voltage. . . . . . . . . . . . . . . -0.5 V to VCC + 0.5 V Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . 2000 V Latchup Current (TA = -40C to +85C) . . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . +4.75 V to +5.25 V Industrial (I) Devices Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . +4.50 V to +5.5 V Operating ranges define those limits between which the functionality of the device is guaranteed. 5-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol VOH VOL VIH VIL IIH IIL IOZH IOZL ISC Parameter Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Test Conditions IOH = -3.2 mA, VCC = Min, VIN = VIH or VIL IOH = -2.5 mA, VCC = Max, VIN = VIH or VIL IOL = 24 mA, VCC = Min, VIN = VIH or VIL (Note 1) Guaranteed Input Logical HIGH Voltage for all Inputs (Note 2) Guaranteed Input Logical LOW Voltage for all Inputs (Note 2) VIN = 5.25 V, VCC = Max (Note 3) VIN = 0 V, VCC = Max (Note 3) VOUT = 5.25 V, VCC = Max, VIN = VIH or VIL (Note 3) VOUT = 0 V, VCC = Max , VIN = VIH or VIL (Note 3) VOUT = 0.5 V, VCC = Max (Note 4) -30 2.0 0.8 10 -10 10 -10 -160 Min 2.4 3.6 0.5 Typ Max Unit V V V V V A A A A mA Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. These are absolute values with respect to device ground, and all overshoots due to system or tester noise are included. 3. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 4. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. VOUT = 0.5 V has been chosen to avoid test problems caused by tester ground degradation. 36 ispMACH 4A Family ABSOLUTE MAXIMUM RATINGS M4A3 Storage Temperature . . . . . . . . . . . . . . . -65C to +150C Ambient Temperature with Power Applied . . . . . . . . . . . . . . . .-55C to +100C Device Junction Temperature . . . . . . . . . . . . . . . +130C Supply Voltage with Respect to Ground . . . . . . . . . . . . . -0.5 V to +4.5 V DC Input Voltage. . . . . . . . . . . . . . . . . . . . -0.5 V to 6.0 V Static Discharge Voltage . . . . . . . . . . . . . . . . . . . . 2000 V Latchup Current (TA = -40C to +85C) . . . . . . . 200 mA Stresses above those listed under Absolute Maximum Ratings may cause permanent device failure. Functionality at or above these limits is not implied. Exposure to Absolute Maximum Ratings for extended periods may affect device reliability. OPERATING RANGES Commercial (C) Devices Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . . . 0C to +70C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V Industrial (I) Devices Ambient Temperature (TA) Operating in Free Air. . . . . . . . . . . . . . . . -40C to +85C Supply Voltage (VCC) with Respect to Ground . . . . . . . . . . . . +3.0 V to +3.6 V Operating ranges define those limits between which the functionality of the device is guaranteed. 3.3-V DC CHARACTERISTICS OVER OPERATING RANGES Parameter Symbol VOH Parameter Description Output HIGH Voltage Test Conditions VCC = Min VIN = VIH or VIL VCC = Min VIN = VIH or VIL (Note 1) IOH = -100 A IOH = -3.2 mA IOL = 100 A IOL = 24 mA 2.0 -0.3 Min VCC - 0.2 2.4 0.2 0.5 5.5 0.8 5 -5 5 -5 -15 -160 Typ Max Unit V V V V V V A A A A mA VOL VIH VIL IIH IIL IOZH IOZL ISC Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input HIGH Leakage Current Input LOW Leakage Current Off-State Output Leakage Current HIGH Off-State Output Leakage Current LOW Output Short-Circuit Current Guaranteed Input Logical HIGH Voltage for all Inputs Guaranteed Input Logical LOW Voltage for all Inputs VIN = 3.6 V, VCC = Max (Note 2) VIN = 0 V, VCC = Max (Note 2) VOUT = 3.6 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0 V, VCC = Max VIN = VIH or VIL (Note 2) VOUT = 0.5 V, VCC = Max (Note 3) Notes: 1. Total IOL for one PAL block should not exceed 64 mA. 2. I/O pin leakage is the worst case of IIL and IOZL (or IIH and IOZH). 3. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Notes: 1. See "MACH Switching Test Circuit" document on the Literature Download page of the Lattice web site. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. ispMACH 4A Family 37 ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 -5 Combinatorial Delay: tPDi tPD Internal combinatorial propagation delay Combinatorial propagation delay Synchronous clock setup time, D-type register Synchronous clock setup time, T-type register Asynchronous clock setup time, D-type register Asynchronous clock setup time, T-type register Synchronous clock hold time Asynchronous clock hold time Synchronous clock to internal output Synchronous clock to output Asynchronous clock to internal output Asynchronous clock to output Synchronous latch setup time Asynchronous latch setup time Synchronous latch hold time Asynchronous latch hold time Transparent latch to internal output Propagation delay through transparent latch to output Synchronous gate to output Asynchronous gate to output Input register setup time 1.5 2.5 3.0 1.5 2.5 3.5 1.5 1.5 2.5 3.5 1.5 4.0 3.0 0.0 3.0 5.5 7.0 3.0 4.5 6.0 7.5 1.5 2.5 3.0 1.5 2.5 3.8 1.5 3.5 5.0 4.0 5.5 4.3 6.0 4.5 6.5 5.0 7.5 7.0 10.0 9.0 12.0 11.0 14.0 ns ns -55 -6 -65 -7 -10 -12 -14 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit Registered Delays: tSS tSST tSA tSAT tHS tHA tCOSi tCOS tCOAi tCOA tSSL tSAL tHSL tHAL tPDLi tPDL 3.0 4.0 2.5 3.0 0.0 2.5 2.5 4.0 5.0 6.5 4.0 3.0 0.0 3.0 5.5 7.0 3.0 4.5 6.0 7.5 2.0 3.0 3.0 2.0 3.0 4.0 1.5 3.5 4.0 2.5 3.0 0.0 2.5 2.5 4.0 5.0 6.5 4.0 3.5 0.0 3.5 5.8 7.5 3.0 4.8 6.0 7.8 2.0 3.0 3.0 2.0 3.0 4.0 2.0 3.5 4.0 2.5 3.0 0.0 2.5 2.8 4.5 5.0 6.8 4.5 3.5 0.0 3.5 6.0 8.0 3.0 5.0 6.0 8.0 2.0 3.0 3.5 2.0 3.0 4.0 2.0 3.5 4.0 3.0 3.5 0.0 3.0 3.0 5.0 5.0 7.0 6.0 4.0 0.0 4.0 7.5 10.0 3.5 6.0 8.5 11.0 2.0 3.0 4.5 2.0 3.0 4.0 2.0 5.0 6.0 3.5 4.5 0.0 3.5 3.0 5.5 6.0 8.5 7.0 4.0 0.0 4.0 9.0 12.0 4.5 7.5 10.0 13.0 2.0 3.0 6.0 2.0 4.0 5.0 2.0 5.5 6.5 4.0 5.0 0.0 4.0 3.0 6.0 8.0 11.0 8.0 5.0 0.0 5.0 11.0 14.0 7.0 10.0 13.0 16.0 2.0 4.0 6.0 7.0 8.0 5.0 6.0 0.0 5.0 3.5 6.5 10.0 13.0 10.0 8.0 0.0 8.0 12.0 15.0 8.0 11.0 15.0 18.0 10.0 11.0 8.0 9.0 0.0 8.0 3.5 6.5 12.0 15.0 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Latched Delays: tGOSi Synchronous gate to internal output tGOS tGOA tSIRS tGOAi Asynchronous gate to internal output Input Register Delays: tHIRS Input register hold time tICOSi Input register clock to internal feedback Input Latch Delays: tSIL tHIL Input latch setup time Input latch hold time Transparent input latch to internal feedback tIGOSi Input latch gate to internal feedback tPDILi 38 ispMACH 4A Family ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -5 Input Register Delays with ZHT Option: tSIRZ Input register setup time - ZHT 6.0 0.0 6.0 0.0 6.0 6.0 0.0 6.0 0.0 6.0 6.0 0.0 6.0 0.0 6.0 6.0 0.0 6.0 0.0 6.0 6.0 0.0 6.0 0.0 6.0 6.0 0.0 6.0 0.0 6.0 6.0 0.0 6.0 0.0 6.0 6.0 0.0 6.0 0.0 6.0 ns ns ns ns ns tHIRZ Input register hold time - ZHT Input Latch Delays with ZHT Option: tSILZ Input latch setup time - ZHT tHILZ Input latch hold time - ZHT tPDIL Transparent input latch to internal feedback - ZHT Zi Output Delays: tBUF tSLW tEA tER tPL Output buffer delay Slow slew rate delay adder Output enable time Output disable time Power-down mode delay adder Asynchronous reset or preset to internal register output Asynchronous reset or preset to register output Asynchronous reset and preset register recovery time Asynchronous reset or preset width Global clock width low Global clock width high Product term clock width low Global gate width low (for low transparent) or high (for high transparent) Product term gate width low (for low transparent) or high (for high transparent) 7.0 7.0 2.0 2.0 3.0 3.0 4.0 1.5 2.5 7.5 7.5 2.5 1.5 2.5 7.5 7.5 2.5 1.8 2.5 8.5 8.5 2.5 2.0 2.5 8.5 8.5 2.5 2.5 2.5 9.5 9.5 2.5 3.0 2.5 10.0 10.0 2.5 3.0 2.5 12.0 12.0 2.5 3.0 2.5 15.0 15.0 2.5 ns ns ns ns ns -55 -6 -65 -7 -10 -12 -14 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit Power Delay: Reset and Preset Delays: tSRi tSR tSRR tSRW tWLS tWHS tWLA 7.5 9.0 7.0 7.0 2.0 2.0 3.0 3.0 4.0 7.7 9.2 7.5 8.0 2.5 2.5 3.5 3.5 4.5 8.0 10.0 7.5 8.0 2.5 2.5 3.5 3.5 4.5 8.0 10.0 8.0 10.0 3.0 3.0 4.0 4.0 5.0 9.5 12.0 8.0 10.0 4.0 4.0 5.0 5.0 5.0 11.0 14.0 10.0 12.0 5.0 5.0 8.0 8.0 6.0 13.0 16.0 15.0 15.0 6.0 6.0 9.0 9.0 6.0 16.0 19.0 ns ns ns ns ns ns ns ns ns Clock/LE Width: tWHA Product term clock width high tGWS tGWA 4.0 3.0 3.0 4.0 4.0 3.0 3.0 4.0 4.5 3.5 3.5 4.5 4.5 3.5 3.5 4.5 5.0 4.0 4.0 5.0 5.0 5.0 5.0 5.0 6.0 6.0 6.0 6.0 9.0 6.0 6.0 6.0 ns ns ns ns tWIRL Input register clock width low tWIRH Input register clock width high tWIL Input latch gate width ispMACH 4A Family 39 ispMACH 4A TIMING PARAMETERS OVER OPERATING RANGES1 (CONTINUED) -5 Frequency: External feedback, D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOS) 143 133 125 167 154 250 111 105 133 125 167 167 125 118 160 148 200 108 102 125 125 143 143 118 111 154 143 200 100 95.2 125 118 143 143 95.2 87.0 125 111 154 83.3 76.9 105 95.2 125 125 87.0 80.0 118 105 125 66.7 62.5 83.3 76.9 100 100 74.1 69.0 95.0 87.0 100 55.6 52.6 66.7 62.5 62.5 83.3 60.6 57.1 74.1 69.0 83.3 43.5 41.7 50.0 47.6 55.6 83.3 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz -55 -6 -65 -7 -10 -12 -14 Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit External feedback, T-type, Min of 1/(tWLS 125 + tWHS) or 1/(tSST + tCOS) fMAXS Internal feedback (fCNT), D-type, Min of 1/(tWLS + tWHS) or 1/(tSS + tCOSi) Internal feedback (fCNT), T-type, Min of 1/(tWLS + tWHS) or 1/(tSST + tCOSi) No feedback2, Min of 1/(tWLS + tWHS), 1/(tSS + tHS) or 1/(tSST + tHS) External feedback, D-type, Min of 1/ (tWLA + tWHA) or 1/(tSA + tCOA) 182 154 250 111 External feedback, T-type, Min of 1/(tWLA 105 + tWHA) or 1/(tSAT + tCOA) fMAXA Internal feedback (fCNTA), D-type, Min of 133 1/(tWLA + tWHA) or 1/(tSA + tCOAi) Internal feedback (fCNTA), T-type, Min of 1/(tWLA + tWHA) or 1/(tSAT + tCOAi) No feedback2, Min of 1/(tWLA + tWHA), 1/(tSA + tHA) or 1/(tSAT + tHA) fMAXI 125 167 Maximum input register frequency, Min 167 of 1/(tWIRH + tWIRL) or 1/(tSIRS + tHIRS) Notes: 1. See "Switching Test Circuit" document on the Literature Download page of the Lattice web site. 2. This parameter does not apply to flip-flops in the emulated mode since the feedback path is required for emulation. CAPACITANCE 1 Parameter Symbol CIN CI/O Parameter Description Input capacitance Output capacitance VIN=2.0 V VOUT=2.0V Test Conditions 3.3 V or 5 V, 25C, 1 MHz 3.3 V or 5 V, 25C, 1 MHz Typ 6 8 Unit pF pF Note: 1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modified where this parameter may be affected. 40 ispMACH 4A Family ICC vs. FREQUENCY These curves represent the typical power consumption for a particular device at system frequency. The selected "typical" pattern is a 16-bit up-down counter. This pattern fills the device and exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type register. Power/Speed are optimized to obtain the highest counter frequency and the lowest power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to lowest power. 400 350 300 250 ICC (mA) 200 M4A-192/96 150 100 50 0 100 140 120 160 180 200 M4A-512/160 M4A-384/160 200 M4A-256/160 M4A-256/128 M4A-192/96 100 M4A-96/48 M4A-128/64 M4A-64/64 M4A-64/32 M4A-32/32 0 100 120 140 160 180 200 20 40 60 80 0 20 40 60 80 0 M4A-96/48 M4A-128/64 M4A-64/64 M4A-64/32 M4A-32/32 VCC = 5 V or 3.3 V, TA = 25 C M4A-512/160 M4A-384/160 M4A-256/160 M4A-256/128 Frequency (MHz) Figure 19. ispMACH 4A ICC Curves at High Speed Mode 250 VCC = 5 V or 3.3 V, TA = 25 C ICC (mA) 150 50 Frequency (MHz) Figure 20. ispMACH 4A ICC Curves at Low Power Mode ispMACH 4A Family 41 44-PIN PLCC CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View 44-Pin PLCC A3 A4 A5 A6 A7 B7 B6 I/O30 D6 B5 I/O29 D5 B4 I/O28 D4 M4A(3,5)-64/32 M4A(3,5)-64/32 6 A2 A1 A0 A2 A1 A0 I/O5 I/O6 I/O7 TDI M4A(3,5)-32/32 CLK0/I0 GND TCK A8 A9 A10 A11 B0 B1 I/O8 I/O9 7 8 9 10 11 12 13 14 15 16 17 54 32 1 44 43 42 41 40 39 38 37 I/O27 I/O26 I/O25 I/O24 TDO GND CLK1/I1 TMS I/O23 I/O22 I/O21 C0 C1 C2 B8 B9 B10 M4A(3,5)-32/32 D3 D2 D1 D0 B3 B2 B1 B0 C 7 I/O31 D7 I/O4 A3 I/O3 A4 I/O2 A5 I/O1 A6 I/O0 A7 GND VCC 36 35 34 33 32 31 30 29 I/O Cell PAL Block B2 I/O10 B3 I/O11 18 19 20 21 22 23 24 25 26 27 28 VCC B4 I/O12 B5 I/O13 B6 I/O14 B7 I/O15 GND C7 I/O16 C6 I/O17 C5 I/O18 C4 I/O19 M4A(3,5)-64/32 C3 I/O20 B11 M4A(3,5)-64/32 A12 A13 A14 A15 B15 B14 B13 B12 17466G-026 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O VCC TDI TCK TMS = Input/Output = Supply Voltage = Test Data In = Test Clock = Test Mode Select TDO = Test Data Out 42 ispMACH 4A Family 44-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View 44-Pin TQFP A3 A4 A5 A6 A7 B7 B6 B5 B4 D7 D6 D5 D4 A2 A1 A0 M4A(3,5)-32/32 A8 A9 A10 A11 I/O5 I/O6 I/O7 TDI CLK0/I0 GND TCK I/O8 B0 I/O9 B1 B2 I/O10 B3 I/O11 A2 A1 A0 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 I/O4 I/O3 I/O2 I/O1 I/O0 GND VCC I/O31 I/O30 I/O29 I/O28 M4A(3,5)-64/32 A3 A4 A5 A6 A7 M4A(3,5)-64/32 C 7 I/O Cell PAL Block 33 32 31 30 29 28 27 26 25 24 23 I/O27 D3 I/O26 D2 I/O25 D1 I/O24 D0 TDO GND CLK1/I1 TMS I/O23 C0 I/O22 C1 I/O21 C2 B3 B2 B1 B0 M4A(3,5)-32/32 B8 B9 B10 M4A(3,5)-64/32 I/O12 I/O13 I/O14 I/O15 VCC GND I/O16 I/O17 I/O18 I/O19 I/O20 12 13 14 15 16 17 18 19 20 21 22 M4A(3,5)-64/32 B4 B5 B6 B7 A12 A13 A14 A15 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O VCC TDI TCK TMS = Input/Output = Supply Voltage = Test Data In = Test Clock = Test Mode Select TDO = Test Data Out ispMACH 4A Family B15 B14 B13 B12 B11 C7 C6 C5 C4 C3 43 48-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-32/32 AND M4A(3,5)-64/32) Top View 48-Pin TQFP A3 A4 A5 A6 A7 A2 A1 A0 M4A(3,5)-32/32 A8 A9 A10 A11 I/O5 I/O6 I/O7 TDI CLK0/I0 NC GND TCK B0 I/O8 B1 I/O9 B2 I/O10 B3 I/O11 A2 A1 A0 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 I/O4 I/O3 I/O2 I/O1 I/O0 GND NC VCC I/O31 I/O30 I/O29 I/O28 M4A(3,5)-64/32 D7 D6 D5 D4 A3 A4 A5 A6 A7 B7 B6 B5 B4 M4A(3,5)-64/32 C 7 I/O Cell PAL Block 36 35 34 33 32 31 30 29 28 27 26 25 I/O27 D3 I/O26 D2 I/O25 D1 I/O24 D0 TDO GND NC CLK1/I1 TMS I/O23 C0 I/O22 C1 I/O21 C2 B3 B2 B1 B0 M4A(3,5)-32/32 B8 B9 B10 M4A(3,5)-64/32 I/O12 I/O13 I/O14 I/O15 VCC NC GND I/O16 I/O17 I/O18 I/O19 I/O20 13 14 15 16 17 18 19 20 21 22 23 24 M4A(3,5)-64/32 A12 A13 A14 A15 B15 B14 B13 B12 B11 C7 C6 C5 C4 C3 B4 B5 B6 B7 17466G-028 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I/O VCC NC TDI TCK TMS = Input/Output = Supply Voltage = No Connect = Test Data In = Test Clock = Test Mode Select TDO = Test Data Out 44 ispMACH 4A Family 100-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-96/48) Top View 100-Pin TQFP A2 A3 A4 A5 A6 A7 GND NC NC I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I7 VCC GND NC NC I6 NC I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 NC NC GND NC TDI NC NC A1 I/O6 A0 I/O7 B0 I/O8 B1 I/O9 B2 I/O10 B3 I/O11 I0/CLK0 VCC GND I1/CLK1 B4 I/O12 B5 I/O13 B6 I/O14 B7 I/O15 C0 I/O16 C1 I/O17 NC NC TMS TCK NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 F7 F6 F5 F4 F3 F2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C 7 I/O Cell PAL Block 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC TDO NC NC NC I/O41 I/O40 I/O39 I/O38 I/O37 I/O36 I5/CLK3 GND VCC I4/CLK2 I/O35 I/O34 I/O33 I/O32 I/O31 I/O30 NC NC NC NC F1 F0 E0 E1 E2 E3 E4 E5 E6 E7 D0 D1 C2 C3 C4 C5 C6 C7 D7 D6 D5 D4 D3 D2 GND NC NC I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 NC I2 NC NC GND VCC I3 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 NC NC GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 17466G-029 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I I/O VCC NC TDI TCK TMS = Input = Input/Output = Supply Voltage = No Connect = Test Data In = Test Clock = Test Mode Select TDO = Test Data Out ispMACH 4A Family 45 100-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-128/64) Top View 100-Pin PQFP A7 A6 A5 A4 A3 A2 A1 A0 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 (10) 100 (9) 99 (8) 98 (7) 97 (6) 96 (5) 95 (4) 94 (3) 93 I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 31 (33) 32 (34) 33 (35) 34 (36) 35 (37) 36 (38) 37 (39) 38 (40) 39 40 41 42 43 (45) 44 (46) 45 (47) 46 (48) 47 (49) 48 (50) 49 (51) 50 (52) GND GND TDI I5 B7 I/O8 B6 I/O9 B5 I/O10 B4 I/O11 B3 I/O12 B2 I/O13 B1 I/O14 B0 I/O15 IO/CLK0 VCC VCC GND GND I1/CLK1 C0 I/O16 C1 I/O17 C2 I/O18 C3 I/O19 C4 I/O20 C5 I/O21 C6 I/O22 C7 I/O23 TMS TCK GND GND 1 2 3 4 (83) 5 (12) 6 (13) 7 (14) 8 (15) 9 (16) 10 (17) 11 (18) 12 (19) 13 (20) 14 15 16 17 18 (23) 19 (24) 20 (25) 21 (26) 22 (27) 23 (28) 24 (29) 25 (30) 26 (31) 27 28 29 30 (82) (81) (80) (79) (78) (77) (76) (75) 92 91 90 89 88 87 86 85 84 83 82 81 H0 H1 H2 H3 H4 H5 H6 H7 C 7 I/O Cell PAL Block 80 79 78 77 (73) 76 (72) 75 (71) 74 (70) 73 (69) 72 (68) 71 (67) 70 (66) 69 (65) 68 67 66 65 64 (62) 63 (61) 62 (60) 61 (59) 60 (58) 59 (57) 58 (56) 57 (55) 56 (54) 55 (41) 54 53 52 51 GND GND TD0 TRST G7 I/O55 G6 I/O54 G5 I/O53 I/O52 G4 I/O51 G3 I/O50 G2 I/O49 G1 I/O48 G0 I4/CLK3 GND GND VCC VCC I3/CLK2 I/O47 F0 F1 I/O46 F2 I/O45 F3 I/O44 F4 I/O43 F5 I/O42 F6 I/O41 F7 I/O40 I2 ENABLE GND GND PIN DESIGNATIONS I/CLK = Input or Clock GND = Ground I I/O VCC TDI TCK TMS = Input = Input/Output = Supply Voltage = Test Data In = Test Clock = Test Mode Select TDO = Test Data Out TRST = Test Reset ENABLE = Program 46 D7 D6 D5 D4 D3 D2 D1 D0 ispMACH 4A Family E0 E1 E2 E3 E4 E5 E6 E7 17466G-031 100-PIN TQFP CONNECTION DIAGRAM (M4A3-64/64 AND M4A(3,5)-128/64) Top View 100-Pin TQFP M4A3-128/64 M4A5-128/64 M4A3-64/64 H0 H1 H2 H3 H4 H5 H6 H7 D0 D2 D4 D6 D8 D10 D12 D14 A7 A6 A5 A4 A3 A2 A1 A0 GND TDI I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 I0/CLK0 VCC GND I1/CLK1 I/O16 B15 I/O17 B13 I/O18 B11 I/O19 B9 I/O20 B7 I/O21 B5 I/O22 B3 I/O23 B1 TMS TCK GND A1 A3 A5 A7 A9 A11 A13 A15 A14 A12 A10 A8 A6 A4 A2 A0 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GND GND I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 VCC GND GND VCC I5 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND GND B7 B6 B5 B4 B3 B2 B1 B0 C0 C1 C2 C3 C4 C5 C6 C7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 C 7 I/O Cell PAL Block 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 GND TDO TRST I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 I4/CLK3 GND VCC I3/CLK2 I/O47 I/O46 I/O45 I/O44 I/O43 I/O42 I/O41 I/O40 ENABLE GND D1 D3 D5 D7 D9 D11 D13 D15 G7 G6 G5 G4 G3 G2 G1 G0 C15 C13 C11 C9 C7 C5 C3 C1 F0 F1 F2 F3 F4 F5 F6 F7 C0 C2 C4 C6 C8 C10 C12 C14 B14 B12 B10 B8 B6 B4 B2 B0 GND GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 VCC GND GND VCC I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 17466G-032a D7 D6 D5 D4 D3 D2 D1 D0 PIN DESIGNATIONS CLK/I = Clock or Input GND = Ground I I/O VCC TDI TCK TMS = Input = Input/Output = Supply Voltage = Test Data In = Test Clock = Test Mode Select TDO = Test Data Out TRST = Test Reset ENABLE = Program ispMACH 4A Family E0 E1 E2 E3 E4 E5 E6 E7 47 100-BALL caBGA CONNECTION DIAGRAM (M4A3-128/64) Bottom View 100-Ball caBGA 10 A GND 9 I/O63 H7 GND 8 I/O60 H4 I/O61 H5 I/O62 H6 GND I/O51 G3 I/O40 F0 I/O42 F2 I/O46 F6 GND I/O36 E4 8 7 I/O57 H1 I5 I/O58 H2 I/O59 H3 I/O54 G6 I/O52 G4 I/O43 F3 GND I/O38 E6 I/O33 E1 7 6 GND 5 GND I/O0 A0 I/O2 A2 I/O5 A5 I/O16 C0 VCC I/O35 E3 I/O24 D0 VCC 4 I/O1 A1 I/O6 A6 GND I/O11 B3 I/O20 C4 I/O22 C6 I/O27 D3 I/O26 D2 I2 I/O25 D1 4 3 I/O4 A4 GND I/O14 B6 I/O10 B2 I/O8 B0 I/O19 C3 GND I/O30 D6 I/O29 D5 I/O28 D4 3 2 I/O7 A7 TDI I/O13 B5 CLK0/I0 1 GND I/O15 B7 I/O12 B4 I/O9 B1 GND A B TRST I/O53 G5 I/O50 G2 CLK3/I3 VCC I/O56 H0 I/O3 A3 VCC I/O48 G0 I/O37 E5 I/O34 E2 I/O32 E0 GND 6 B C TDO I/O55 G7 I/O49 G1 VCC C D D E VCC I/O17 C1 I/O23 C7 TCK E F GND I/O41 F1 I/O44 F4 I/O47 F7 GND 10 CLK1/I1 F I/O18 C2 I/O21 C5 TMS G CLK2/I2 I/O45 F5 ENABLE I/O39 E7 9 G H H J GND I/O31 D7 2 J K GND 5 GND 1 K PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block 17466G-100cabga 48 ispMACH 4A Family 144-PIN TQFP CONNECTION DIAGRAM (M4A(3,5)-192/96) Top View 144-Pin TQFP B7 B6 B5 B4 B3 B2 B1 B0 A7 A6 A5 A4 A3 A2 A1 A0 L0 L1 L2 L3 L4 L5 L6 L7 D7 D6 D5 D4 D3 D2 D1 D0 C7 C6 C5 C4 C3 C2 C1 C0 E7 E6 E5 E4 E3 E2 E1 E0 GND TDI I/O0 I/O1 I/O2 I/O3 I/O4 I/O5 I/O6 I/O7 I2 I3 VCC GND I4 I/O8 I/O9 I/O10 I/O11 I/O12 I/O13 I/O14 I/O15 GND VCC I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 TMS TCK GND 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 I1 I0 CLK0 GND VCC CLK3 I15 I14 I13 I/O79 I/O78 I/O77 I/O76 I/O75 I/O74 I/O73 I/O72 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 C 7 I/O Cell PAL Block 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 GND TDO NC I/O71 I/O70 I/O69 I/O68 I/O67 I/O66 I/O65 I/O64 I12 VCC GND I11 I10 I/O63 I/O62 I/O61 I/O60 I/O59 I/O58 I/O57 I/O56 GND VCC I/O55 I/O54 I/O53 I/O52 I/O51 I/O50 I/O49 I/O48 NC GND K0 K1 K2 K3 K4 K5 K6 K7 J0 J1 J2 J3 J4 J5 J6 J7 I0 I1 I2 I3 I4 I5 I6 I7 G0 G1 G2 G3 G4 G5 G6 G7 H0 H1 H2 H3 H4 H5 H6 H7 F7 F6 F5 F4 F3 F2 F1 F0 GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I5 I6 I7 CLK1 GND VCC CLK2 I8 I9 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 VCC GND I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 17466G-033 PIN DESIGNATIONS CLK = Clock GND = Ground I I/O VCC TDI TCK TMS = Input = Input/Output = Supply Voltage = Test Data In = Test Clock = Test Mode Select TDO = Test Data Out ispMACH 4A Family 49 144-BALL fpBGA CONNECTION DIAGRAM (M4A3-192/96) Bottom View 144-Ball fpBGA 12 A B C D E F G H J K L M GND 11 I/O95 L7 I/O94 L6 TDO 10 I/O91 L3 I/O90 L2 I/O93 L5 I/O80 K0 I/O85 K5 GND 9 I13 I/O88 L0 I14 8 GBCLK3 7 I0 6 I/O2 A2 I/O3 A3 I/O4 A4 VCC 5 I/O6 A6 I/O7 A7 GND 4 I/O8 B0 I/O10 B2 I/O12 B4 I/O29 D5 I/O23 C7 I/O19 C3 I/O38 E6 I/O33 E1 I/O44 F4 I6 3 I/O13 B5 I/O14 B6 I/O30 D6 I2 2 I/O15 B7 I/O31 D7 I/O27 D3 I/O25 D1 GND 1 GND A B C D E F G H J K L M GND VCC I1 TDI GND GND I/O0 A0 I/O1 A1 I/O5 A5 I15 I/O28 D4 I/O24 D0 VCC I/O84 K4 I12 I/O82 K2 I/O87 K7 I11 I/O92 L4 I/O81 K1 I/086 K6 I/O72 J0 I/O76 J4 I/O69 I5 I/O60 H4 I/O58 H2 I/O56 H0 GBCLK0 I/O11 B3 I/O26 D2 GND I/O89 L1 I/O83 K3 VCC I/O9 B1 I3 I4 I10 I/O20 C4 I/O16 C0 I/O37 E5 I/O32 E0 I/O45 F5 I/O42 F2 I/O43 F3 I/O21 C5 I/O17 C1 I/O39 E7 I/O34 E2 TCK I/O22 C6 I/O18 C2 VCC I/O75 J3 I/O79 J7 I/O64 I0 I/O68 I4 GND I/O74 J2 I/O78 J6 I/O65 I1 I/O67 I3 I/O71 I7 I/O63 H7 I/O73 J1 I/O77 J5 VCC GND I7 I/O35 E3 I/O41 F1 GBCLK2 I/O66 I2 I/O59 H3 GND I/O57 H1 VCC I/O53 G5 I/O49 G1 I/O48 G0 I9 I/O36 E4 TMS I/O70 I6 I/O62 H6 I/O61 H5 I/O52 G4 I/O51 G3 I/O50 G2 VCC I/O55 G7 I/O54 G6 GND I/O40 F0 I5 I/O46 F6 I/O47 F7 GND GND I8 GBCLK1 GND 12 11 10 9 8 7 6 5 4 3 2 1 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block m4a3.192.96_144bga 50 ispMACH 4A Family 208-PIN PQFP CONNECTION DIAGRAM (M4A(3,5)-256/128 AND M4A3-256/160) Top View 208-Pin PQFP O8 O9 O10 O11 O12 O13 O14 O15 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A14 A12 P12 P14 O0 O1 O2 O3 O4 O5 O6 O7 A6 A4 P4 P6 O0 O1 O2 O3 O4 O5 O6 O7 B7 B6 B5 B4 B3 B2 B1 B0 A7 A6 A5 A4 A3 A2 A1 A0 P0 P1 P2 P3 P4 P5 P6 P7 GND I/O19 I/O18 I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 GND VCC I/O11 I/O10 I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 CLK0 VCC GND I/O1 I/O0 I/O159 I/O158 GND VCC CLK3 I/O157 I/O156 I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 VCC GND I/O147 I/O146 I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 GND M4A3-256/160 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 GND I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 I/O9 I/O8 GND VCC I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 I1 I0 CLK0 VCC GND GND VCC VCC GND GND VCC CLK3 I13 I12 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 I/O120 VCC GND I/O119 I/O118 I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 GND M4A(3, 5)256/128 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 C0 D14 D12 D6 D4 E0 E2 E6 E10 F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 GND TDI I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 I/O26 I/O27 VCC GND I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 GND VCC I/O38 I/O39 I/O40 I/O41 I/O42 GND I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 I/O50 I/O51 GND VCC I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 I/O58 I/O59 TMS TCK GND C7 C6 C5 C4 C3 C2 C1 C0 D7 D6 D5 D4 D3 D2 D1 D0 E0 E1 E2 E3 E4 E5 E6 E7 F0 F1 F2 F3 F4 F5 F6 F7 GND TDI I/O16 I/O17 I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 VCC GND I/O24 I/O25 I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I2 I3 GND VCC VCC GND GND VCC VCC GND I4 I/O32 I/O33 I/O34 I/O35 I/O36 I/O37 I/O38 I/O39 GND VCC I/O40 I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 TMS TCK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 156 155 RECOMMEND TO TIE TO VCC 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 I/O Cell 124 123 PAL Block 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 RECOMMEND TO TIE TO GND 106 105 GND TDO TRST I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 I/O105 I/O104 VCC GND I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 I/O97 I/O96 I11 GND VCC VCC GND GND VCC VCC GND I10 I9 I/O95 I/O94 I/O93 I/O92 I/O91 I/O90 I/O89 I/O88 GND VCC I/O87 I/O86 I/O85 I/O84 I/O83 I/O82 I/O81 I/O80 ENABLE GND N7 N6 N5 N4 N3 N2 N1 N0 M7 M6 M5 M4 M3 M2 M1 M0 L0 L1 L2 L3 L4 L5 L6 L7 K0 K1 K2 K3 K4 K5 K6 K7 GND TDO NC I/O139 I/O138 I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 VCC GND I/O131 I/O130 I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 GND I/O122 I/O121 I/O120 I/O119 I/O118 VCC GND I/O117 I/O116 I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 GND VCC I/O107 I/O106 I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 NC GND N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 N5 N4 N3 N2 N1 N0 M10 M6 M2 M0 L4 L6 L12 L14 K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 G7 G6 G5 G4 G3 G2 G1 G0 H7 H6 H5 H4 H3 H2 H1 H0 G15 G14 G13 G12 G11 G10 G9 G8 I12 I14 J0 J1 J2 J3 J4 J5 J6 J7 G7 G6 G5 G4 G3 G2 G1 G0 H14 H12 J8 J9 J10 J11 J12 J13 J14 J15 H6 H4 I4 I6 GND I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 I/O66 I/O67 GND VCC I/O68 I/O69 I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 CLK1 VCC GND I/O78 I/O79 I/O80 I/O81 GND VCC CLK2 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 I/O90 I/O91 VCC GND I/O92 I/O93 I/O94 I/O95 I/O96 I/O97 I/O98 I/O99 GND J0 J1 J2 J3 J4 J5 J6 J7 I0 I1 I2 I3 I4 I5 I6 I7 GND I/O48 I/O49 I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 GND VCC I/O56 I/O57 I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I5 I6 CLK1 VCC GND GND VCC VCC GND GND VCC CLK2 I7 I8 I/O64 I/O66 I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 VCC GND I/O72 I/O73 I/O74 I/O75 I/O76 I/O77 I/O78 I/O79 GND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 17466G-044 ispMACH 4A Family 51 208-PIN PQFP CONNECTION DIAGRAM (M4A3-384/160 AND M4A3-512/160) Top View 208-Pin PQFP XO0 XO1 XO2 XO3 XO4 XO5 XO6 XO7 XP6 XP7 XN0 XN1 XN2 XN3 XN4 XN5 XN6 XN7 A4 A1 XP1 XP4 XH6 XH7 XE0 XE1 XE2 XE3 XE4 XE5 XE6 XE7 XG0 XG1 XG2 XG3 XG4 XG5 XG6 XG7 B7 B6 B5 B4 B3 B2 B1 B0 D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A4 A1 XH1 XH4 GND I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 GND VCC I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLK0 VCC GND I/O159 I/O158 I/O157 I/O156 GND VCC CLK3 I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 VCC GND I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 I/O139 I/O138 GND C7 C6 C5 C4 C3 C2 C1 C0 A7 A6 B7 B6 B5 B4 B3 B2 B1 B0 M4A3-512/160 M4A3-384/160 F7 F6 F5 F4 F3 F2 F1 F0 G7 G6 G5 G4 G3 G2 G1 G0 E7 E5 E2 E0 L0 L2 L3 L5 J0 J1 J2 J3 J4 J5 J6 J7 K0 K1 K2 K3 K4 K5 K6 K7 GND TDI I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 VCC GND I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 GND VCC I/O36 I/O37 I/O38 I/O39 I/O40 GND I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 GND VCC I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 TMS TCK GND 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 GND I/O17 I/O16 I/O15 I/O14 I/O13 I/O12 I/O11 I/O10 GND VCC I/O9 I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0 CLK0 VCC GND I/O159 I/O158 I/O157 I/O156 GND VCC CLK3 I/O155 I/O154 I/O153 I/O152 I/O151 I/O150 I/O149 I/O148 I/O147 I/O146 VCC GND I/O145 I/O144 I/O143 I/O142 I/O141 I/O140 I/O139 I/O138 GND C7 C6 C5 C4 C3 C2 C1 C0 F7 F6 F5 F4 F3 F2 F1 F0 E7 E5 E2 E0 H0 H2 H3 H5 G0 G1 G2 G3 G4 G5 G6 G7 J0 J1 J2 J3 J4 J5 J6 J7 GND TDI I/O18 I/O19 I/O20 I/O21 I/O22 I/O23 I/O24 I/O25 VCC GND I/O26 I/O27 I/O28 I/O29 I/O30 I/O31 I/O32 I/O33 I/O34 I/O35 GND VCC I/O36 I/O37 I/O38 I/O39 I/O40 GND I/O41 I/O42 I/O43 I/O44 I/O45 I/O46 I/O47 I/O48 I/O49 GND VCC I/O50 I/O51 I/O52 I/O53 I/O54 I/O55 I/O56 I/O57 TMS TCK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 156 155 RECOMMEND TO TIE TO VCC 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 I/O Cell 124 123 PAL Block 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 RECOMMEND TO TIE TO GND 106 105 GND TDO NC I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 VCC GND I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 GND I/O120 I/O119 I/O118 I/O117 I/O116 VCC GND I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 GND VCC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 NC GND XF7 XF6 XF5 XF4 XF3 XF2 XF1 XF0 XC7 XC6 XC5 XC4 XC3 XC2 XC1 XC0 XD5 XD3 XD2 XD0 XA0 XA2 XA5 XA7 XB0 XB1 XB2 XB3 XB4 XB5 XB6 XB7 O0 O1 O2 O3 O4 O5 O6 O7 GND TDO NC I/O137 I/O136 I/O135 I/O134 I/O133 I/O132 I/O131 I/O130 VCC GND I/O129 I/O128 I/O127 I/O126 I/O125 I/O124 I/O123 I/O122 I/O121 GND I/O120 I/O119 I/O118 I/O117 I/O116 VCC GND I/O115 I/O114 I/O113 I/O112 I/O111 I/O110 I/O109 I/O108 I/O107 I/O106 GND VCC I/O105 I/O104 I/O103 I/O102 I/O101 I/O100 I/O99 I/O98 NC GND XK7 XK6 XK5 XK4 XK3 XK2 XK1 XK0 XJ7 XJ6 XJ5 XJ4 XJ3 XJ2 XJ1 XJ0 XL5 XL3 XL2 XL0 XE0 XE2 XE5 XE7 XG0 XG1 XG2 XG3 XG4 XG5 XG6 XG7 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 L4 L1 M1 M4 M6 M7 P0 P1 P2 P3 P4 P5 P6 P7 O7 O6 O5 O4 O3 O2 O1 O0 N7 N6 N5 N4 N3 N2 N1 N0 P7 P6 P4 P1 XA1 XA4 XA6 XA7 XC0 XC1 XC2 XC3 XC4 XC5 XC6 XC7 XB0 XB1 XB2 XB3 XB4 XB5 XB6 XB7 GND I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 GND VCC I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 CLK1 VCC GND I/O76 I/O77 I/O78 I/O79 GND VCC CLK2 I/O80 I/O81 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 VCC GND I/O90 I/O91 I/O92 I/O93 I/O94 I/O95 I/O96 I/O97 GND N0 N1 N2 N3 N4 N5 N6 N7 K7 K6 K5 K4 K3 K2 K1 K0 I7 I6 I5 I4 I3 I2 I1 I0 L7 L6 GND I/O58 I/O59 I/O60 I/O61 I/O62 I/O63 I/O64 I/O65 GND VCC I/O66 I/O67 I/O68 I/O69 I/O70 I/O71 I/O72 I/O73 I/O74 I/O75 CLK1 VCC GND I/O76 I/O77 I/O78 I/O79 GND VCC CLK2 I/O80 I/O81 I/O82 I/O83 I/O84 I/O85 I/O86 I/O87 I/O88 I/O89 VCC GND I/O90 I/O91 I/O92 I/O93 I/O94 I/O95 I/O96 I/O97 GND 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 17466Ga-044 52 ispMACH 4A Family 256-BALL BGA CONNECTION DIAGRAM (M4A(3,5)-256/128) Bottom View 256-Ball BGA 20 A GND 19 N/C I/O113 O6 N/C I/O117 O2 I/O119 O0 I/O122 P5 I/O125 P2 I/O127 P0 N/C CLK3 18 GND 17 I/O108 N4 I/O109 N5 TRST 16 I/O105 N1 I/O106 N2 I/O111 N7 VCC 15 GND I/O103 M7 I/O107 N3 I/O110 N6 14 I/O100 M4 I/O102 M6 I/O104 N0 VCC 13 I/O96 M0 I/O98 M2 I/O101 M5 N/C 12 GND 11 GND 10 GND 9 GND 8 I/O95 L0 I/O93 L2 I/O90 L5 N/C 7 I/O91 L4 I/O89 L6 I/O86 K1 VCC 6 GND I/O88 L7 I/O84 K3 I/O81 K6 5 I/O87 K0 I/O85 K2 I/O80 K7 VCC 4 N/C I/O83 K4 ENABLE 3 GND I/O82 K5 VCC I/O79 J7 I/O77 J5 I/O73 J1 I/O70 I6 I/O66 I2 N/C N/C 2 GND 1 GND A B C GND I/O116 O3 I/O120 P7 I/O123 P4 GND N/C VCC I/O112 O7 I/O114 O5 I/O118 O1 I/O121 P6 I/O126 P1 N/C N/C N/C I/O97 M1 I/O99 M3 I11 N/C N/C I10 N/C I/O94 L1 I/O92 L3 N/C I/O78 J6 I/O75 J3 I/O72 J0 I/O69 I5 I/O65 I1 I/O64 I0 N/C CLK2 GND I/O74 J2 I/O71 I7 I/O68 I4 GND B C D E F VCC TDI I/O115 O4 VCC I/O124 P3 I13 N/C N/C I9 VCC TDO I/O76 J4 VCC I/O67 I3 I7 N/C D E F G H I12 GND PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program I8 GND G H J K N/C GND N/C N/C J K L N/C CLK0 N/C N/C N/C N/C CLK1 I/O63 H0 I/O59 H4 I/O58 H5 I/O56 H7 I/O55 G0 I/O53 G2 I/O52 G3 I/O49 G6 N/C 2 GND I/O62 H1 GND I5 GND L M N/C N/C I/O0 A0 I/O1 A1 I/O5 A5 I/O8 B0 I/O11 B3 I/O13 B5 I/O14 B6 GND 19 N/C I/O2 A2 I/O6 A6 I/O9 B1 I/O12 B4 I/O15 B7 VCC I0 I/O3 A3 VCC N/C C 7 I/O Cell PAL Block I6 I/O60 H3 VCC I/O51 G4 TMS N/C I/O61 H2 I/O57 H6 I/O54 G1 I/O50 G5 I/O48 G7 VCC M N P R GND I1 GND I/O4 A4 I/O7 A7 I/O10 B2 GND N P R T TCK I/O18 C5 I/O21 C2 I/O22 C1 GND 15 I/O24 D7 I/O27 D4 I/O28 D3 I/O30 D1 13 I/O29 D2 I/O31 D0 N/C I/O35 E3 I/O33 E1 N/C N/C T U V VCC I/O16 C7 N/C VCC I/O17 C6 I/O19 C4 I/O20 C3 16 VCC I/O23 C0 I/O25 D6 I/O26 D5 14 I2 I3 N/C N/C N/C I/O37 E5 I/O34 E2 I/O32 E0 8 VCC I/O41 F1 I/O38 E6 I/O36 E4 7 N/C I/O43 F3 I/O39 E7 GND 6 VCC I/O46 F6 I/O42 F2 I/O40 F0 5 VCC I/O47 F7 I/O45 F5 I/O44 F4 4 N/C N/C U V W N/C N/C I4 N/C GND W Y GND 20 GND 18 N/C 17 GND 12 GND 11 GND 10 GND 9 GND 3 GND 1 Y 17466G-045 ispMACH 4A Family 53 256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/192) Bottom View 256-Ball fpBGA 16 A B C D E F G H J K L M N P R T I/O167 N15 I/O165 N13 I/O163 N11 I/O158 N6 I/O156 N4 I/O152 N0 I/O147 M6 I/O144 M0 I/O138 L4 I/O143 L14 I/O124 K4 I/O128 K8 I/O132 K12 I/O134 K14 I/O116 J12 I/O114 J10 15 I/O181 O13 I/O166 N14 I/O164 N12 I/O159 N7 NC I/O157 N5 I/O150 M12 I/O146 M4 I/O139 L6 I/O120 K0 I/O125 K5 I/O129 K9 I/O133 K13 I/O117 J13 I/O115 J11 I/O113 J9 14 I/O180 O12 I/O182 O14 NC TDO I/O162 N10 I/O155 N3 I/O149 M10 I/145 OM2 I/O140 L8 I/O121 K1 I/O127 K7 I/O131 K11 I/O135 K15 I/O118 J14 I/O112 J8 I/O110 J6 13 I/O177 O9 I/O179 O11 I/O183 O15 GND VCC GND VCC GND GND VCC GND GND VCC I/O119 J15 I/O111 J7 I/O109 J5 12 I/O174 O6 I/O175 O7 I/O178 O10 GND I/O160 N8 I/O154 N2 I/O148 M8 I/O136 L0 I/O142 L12 I/O123 K3 I/O130 K10 I/O107 J3 GND I/O108 J4 I/O104 J0 11 I/O172 O4 I/O173 O5 I/O170 O2 VCC I/O161 N9 I/O153 N1 I/O151 M14 I/O137 L2 I/O141 L10 I/O122 K2 I/O126 K6 I/O105 J1 VCC I/O106 J2 I/O102 I12 10 I/O191 P14 I/O168 O0 I/O171 O3 GND 9 I/O186 P4 I/O187 P6 I/O189 P10 VCC 8 I/O1 A2 I/O0 A0 I/O184 P0 GND 7 I/O3 A6 I/O5 A10 I/O6 A12 GND I/O2 A4 I/O4 A8 VCC GND GND VCC I/O77 G5 I/O80 G8 GND I/O94 H12 I/O72 G0 I/O95 H14 6 GCLK0 I/O7 A14 I/O12 B4 VCC I/O8 B0 I/O11 B3 I/O33 C9 I/O27 C3 I/O46 D12 I/O41 D2 I/O52 E8 I/O83 G11 VCC I/O79 G7 I/O76 G4 I/O73 G1 5 I/O9 B1 I/O10 B2 I/O14 B6 GND NC I/O34 C10 I/O28 C4 I/O24 C0 I/O45 D10 I/O40 D0 I/O51 E6 I/O53 E10 GND I/O84 G12 I/O81 G9 I/O78 G6 4 I/O13 B5 I/O16 B8 I/O23 B15 VCC GND VCC GND VCC GND VCC GND VCC GND I/O87 G15 I/O85 G13 I/O82 G10 3 I/O15 B7 I/O19 B11 I/O22 B14 I/O17 B9 I/O36 C12 I/O32 C8 I/O26 C2 I/O44 D8 I/O49 E2 I/O55 E14 I/O59 F3 I/O68 F12 TCK TMS I/O71 F15 I/O86 G14 2 I/O18 B10 I/O21 B13 TDI I/O38 C14 I/O35 C11 I/O30 C6 I/O25 C1 I/O43 D6 I/O48 E0 I/O54 E12 I/O60 F4 I/O63 F7 I/O64 F8 I/O65 F9 I/O67 F11 I/O70 F14 1 I/O20 B12 NC I/O39 C15 I/O37 C13 I/O31 C7 I/O29 C5 I/O47 D14 I/O42 D4 I/O50 E4 I/O56 F0 I/O57 F1 I/O58 F2 I/O61 F5 I/O62 F6 I/O66 F10 I/O69 F13 A B C D E F G H J K L M N P R T I/O190 GCLK3 I/O188 P12 P8 I/O176 O8 VCC GND GND VCC I/O98 I4 I/O100 I8 GND I/O101 I10 I/O99 I6 I/O97 I2 I/O169 O1 GND VCC VCC GND I/O91 H6 I/O90 H4 VCC I/O89 H2 I/O96 I0 I/O88 H0 I/O185 P2 GND VCC VCC GND I/O75 G3 I/O74 G2 GND I/O93 H10 I/O92 H8 GCLK1 I/O103 GCLK2 I14 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block 17466G-047 54 ispMACH 4A Family 256-BALL BGA CONNECTION DIAGRAM - (M4A3-384/192) Bottom View 256-Ball BGA 20 A GND 19 I/O11 XF7 I/O12 XG7 I/O13 XG5 I/O14 XG3 I/O15 XG0 I/O16 XE1 I/O17 XE4 I/O18 XH5 I/O19 XH1 CLK3 18 GND I/O28 XF5 VCC I/O29 XG4 I/O30 XG1 I/O31 XE6 I/O32 XE5 I/O33 XE2 I/O34 XH4 I/O35 XH2 I/O36 A0 I/O37 A5 I/O38 D0 I/O39 D4 I/O40 D6 I/O41 B7 I/O42 B6 VCC I/O43 C6 GND 18 17 I/O44 XF6 I/O45 XF3 I/O46 XF4 VCC TDI I/O47 XG2 VCC I/O48 XE3 I/O49 XH7 I/O50 XH3 I/O51 A1 I/O52 A6 I/O53 D1 VCC I/O54 D7 TCK 16 I/O58 XC6 I/O59 XC7 I/O60 XF2 VCC 15 GND I/O64 XC5 I/O65 XF1 I/O66 XF0 14 I/O70 XC2 I/O71 XC3 I/O72 XC4 VCC 13 I/O76 XD6 I/O77 XD7 I/O78 XC0 I/O79 XC1 12 GND I/O84 XD5 I/O85 XD4 I/O86 XD3 11 GND I/O90 XD2 I/O91 XD1 I/O92 XD0 10 GND I/O96 XA0 I/O97 XA1 I/O98 XA2 9 GND I/O102 XA3 I/O103 XA4 I/O104 XA7 8 I/O108 XA5 I/O109 XA6 I/O110 XB2 I/O111 XB3 7 I/O116 XB0 I/O117 XB1 I/O118 XB5 VCC 6 GND I/O122 XB4 I/O123 O0 I/O124 O2 5 I/O128 XB7 I/O129 XB6 I/O130 O1 VCC 4 I/O134 O3 I/O135 O4 I/O136 O5 VCC TDO I/O137 N1 VCC 3 GND I/O148 O6 VCC I/O149 N4 I/O150 N2 I/O151 N0 I/O152 P4 I/O153 P1 I/O154 M5 I/O155 M1 I/O156 L4 I/O157 L5 I/O158 I0 I/O159 I4 I/O160 K0 I/O161 K4 I/O162 K7 VCC I/O163 J6 GND 3 2 GND I/O164 O7 I/O165 N7 I/O166 N5 I/O167 N3 I/O168 P5 I/O169 P3 I/O170 P0 I/O171 M4 CLK2 1 GND A B GND I/O0 XG6 I/O1 XE7 I/O2 XE0 GND I/O3 XH6 GND I/O4 XH0 GND I/O5 A2 I/O6 A4 GND I/O7 D2 GND I/O8 B3 I/O9 B4 I/O10 B5 GND GND 20 GND I/O181 N6 I/O182 P7 I/O183 P6 GND I/O184 M7 GND I/O185 M3 I/O186 M2 GND I/O187 L1 GND I/O188 L2 GND I/O189 I2 I/O190 I6 I/O191 I7 GND GND 1 B C D E C D E F G F G PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out H J K I/O138 P2 I/O139 M6 I/O140 M0 I/O141 L3 H J K L M N CLK0 I/O20 A3 I/O21 A7 I/O22 D3 I/O23 D5 I/O24 B0 I/O25 B1 I/O26 B2 I/O27 C7 GND 19 CLK1 I/O172 L0 I/O173 L7 I/O174 I1 I/O175 I3 I/O176 K1 I/O177 K2 I/O178 K3 I/O179 J7 I/O180 K6 2 L M N C 7 I/O Cell PAL Block I/O142 L6 I/O143 I5 VCC I/O144 K5 TMS P R P R T T U V W Y VCC I/O55 C5 I/O56 C3 I/O57 C4 17 VCC I/O61 C2 I/O62 F7 I/O63 F6 16 I/O67 C0 I/O68 C1 I/O69 F5 GND 15 VCC I/O73 F4 I/O74 F3 I/O75 F2 14 I/O80 F0 I/O81 F1 I/O82 E7 I/O83 E6 13 I/O87 E5 I/O88 E4 I/O89 E3 GND 12 I/O93 E2 I/O94 E1 I/O95 E0 GND 11 I/O99 H2 I/O100 H1 I/O101 H0 GND 10 I/O105 H5 I/O106 H4 I/O107 H3 GND 9 I/O112 G0 I/O113 G1 I/O114 H7 I/O115 H6 8 VCC I/O119 G4 I/O120 G3 I/O121 G2 7 I/O125 J1 I/O126 J0 I/O127 G5 GND 6 VCC I/O131 J2 I/O132 G7 I/O133 G6 5 VCC I/O145 J5 I/O146 J4 I/O147 J3 4 U V W Y 17466G-046 ispMACH 4A Family 55 256-BALL fpBGA CONNECTION DIAGRAM (M4A3-256/128) Bottom View 256-Ball fpBGA 16 A B C D E F G H J K L M N P R T TRST 15 I/O117 O5 I/O111 N7 I/O109 N5 I/O104 N0 NC 14 I/O116 O4 I/O118 O6 NC 13 I/O113 O1 I/O115 O3 I/O119 O7 GND 12 I/O126 P6 I/O127 P7 I/O114 O2 GND 11 I/O124 P4 I/O125 P5 I/O122 P2 VCC 10 I12 9 NC 8 NC 7 NC 6 CLK0 5 I/O1 A1 I/O2 A2 I/O6 A6 GND 4 I/O5 A5 I/O8 B0 I/O5 B7 VCC 3 I/O7 A7 I/O11 B3 I/O14 B6 I/O9 B1 I/O20 C4 I/O16 C0 I/O26 D2 NC 2 I/O10 B2 I/O13 B5 TDI 1 I/O12 B4 NC A B C D E F G H J K L M N P R T I/O110 N6 I/O108 N4 NC I/O120 P0 I/O123 P3 GND NC NC NC I1 NC NC I0 I/O4 A4 VCC I/O23 C7 I/O21 C5 I/O31 D7 I/O29 D5 I2 TDO VCC GND GND I/O22 C6 I/O19 C3 I/O30 D6 I/O25 D1 NC I/O102 M6 I/O98 M2 NC I/O107 N3 I/O101 M5 I11 VCC I/O105 N1 I/O100 M4 NC I/O106 N2 I/O99 M3 I/O97 M1 I/O90 L2 I/O94 L6 NC I13 CLK3 NC NC I/O0 A0 I/O3 A3 I/O17 C1 I/O27 D3 I3 NC GND I/O103 M7 I/O96 M0 I10 GND I/O112 O0 VCC I/O121 P1 GND NC NC I/O18 C2 I/O28 D4 I/O24 D0 NC VCC VCC GND VCC GND I/O88 L0 I/O91 L3 NC I9 GND I/O89 L1 I/O95 L7 NC GND VCC VCC GND VCC NC I/O92 L4 NC I/O93 L5 NC GND GND VCC VCC GND GND NC NC NC VCC VCC GND GND VCC NC NC VCC I4 NC I/O32 E0 I/O33 E1 I/O34 E2 I/O37 E5 I/O38 E6 I/O42 F2 I/O45 F5 NC NC I/O80 K0 I/O84 K4 TENB GND I/O83 K3 I/O67 I3 GND NC NC NC I/O59 H3 I/O58 H2 GND I/O61 H5 I/O48 G0 GND NC NC GND I/O35 E3 I/O44 F4 TCK I/O36 E4 I/O39 E7 I/O40 F0 I/O41 F1 I/O43 F3 I/O46 F6 I/O81 K1 I/O85 K5 I/O87 K7 I/O76 J4 I/O74 J2 I/O82 K2 I/O86 K6 I/O77 J5 I/O75 J3 I/O73 J1 GND I/O65 I1 VCC NC NC I/O51 G3 VCC NC VCC VCC GND VCC GND GND I/O78 J6 I/O72 J0 I/O70 I6 I/O79 J7 I/O71 I7 I/O69 I5 I/O68 I4 I/O64 I0 I8 I/O66 I2 I7 NC NC NC I6 I/O63 H7 I/O60 H4 I/O57 H1 I/O52 G4 I/O49 G1 I/O62 H6 I/O55 G7 I/O53 G5 I/O50 G2 TMS NC NC NC I/O56 H0 I5 I/O47 F7 I/O54 G6 CLK2 NC NC CLK1 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block m4a3.256.128_256bga 56 ispMACH 4A Family 256-BALL fpBGA CONNECTION DIAGRAM (M4A3-384/192) Bottom View 256-Ball fpBGA 16 A B C D E F G H J K L M N P R T 15 14 13 12 11 10 9 8 I/O1 A1 I/O0 A0 7 I/O3 A3 I/O5 A5 I/O6 A6 GND I/O2 A2 I/O4 A4 VCC 6 CLK0 I/O7 A7 I/O28 D4 VCC I/O24 D0 I/O27 D3 I/O17 C1 I/O43 F3 I/O38 E6 I/O33 E1 I/O60 H4 I/O83 K3 VCC I/O71 I7 I/O68 I4 I/O65 I1 5 I/O25 D1 I/O26 D2 I/O30 D6 GND 4 I/O29 D5 I/O8 B0 I/O15 B7 VCC 3 I/O31 D7 I/O11 B3 I/O14 B6 I/O9 B1 I/O20 C4 I/O16 C0 I/O42 F2 I/O36 E4 I/O57 H1 I/O63 H7 I/O51 G3 I/O76 J4 TCK 2 I/O10 B2 I/O13 B5 TDI I/O22 C6 I/O19 C3 I/O46 F6 I/O41 F1 I/O35 E3 I/O56 H0 I/O62 H6 I/O52 G4 I/O55 G7 I/O72 J0 I/O73 J1 I/O75 J3 I/O78 J6 1 I/O12 B4 N/C I/O23 C7 I/O21 C5 I/O47 F7 I/O45 F5 I/O39 E7 I/O34 E2 I/O58 H2 I/O48 G0 I/O49 G1 I/O50 G2 I/O53 G5 I/O54 G6 I/O74 J2 I/O77 J5 I/O175 I/O181 I/O180 I/O177 I/O166 I/O164 I/O191 I/O186 FX7 GX5 GX4 GX1 EX6 EX4 HX7 HX2 I/O173 I/O174 I/O182 I/O179 I/O167 I/O165 I/O160 I/O187 FX5 FX6 GX6 GX3 EX7 EX5 EX0 HX3 I/O171 I/O172 FX3 FX4 I/O150 I/O151 CX6 CX7 I/O148 CX4 N/C N/C A B C D E F G H J K L M N P R T I/O183 I/O178 I/O162 I/O163 I/O189 I/O184 GX7 GX2 EX2 EX3 HX5 HX0 GND GND I/O168 FX0 VCC 169 FX1 GND I/O190 HX6 VCC GND I/O188 HX4 TDO I/O170 FX2 VCC CLK3 N/C I/O18 C2 I/O44 F4 I/O40 F0 I/O37 E5 I/O32 E0 I/O59 H3 I/O61 H5 GND I/O84 K4 I/O81 K1 I/O70 I6 GND I/O144 I/O149 I/O147 CX0 CX5 CX3 I/O155 I/O158 I/O157 DX3 DX6 DX5 I/O152 I/O154 I/O153 DX0 DX2 DX1 I/O130 I/O131 I/O132 AX2 AX3 AX4 I/O135 I/O136 I/O137 AX7 BX0 BX1 I/O140 I/O141 I/O143 BX4 BX5 BX7 I/O112 I/O113 I/O115 O0 O1 O3 I/O116 I/O117 I/O119 O4 O5 O7 GND I/O146 I/O145 I/O176 I/O161 I/O185 CX2 CX1 GX0 EX1 HX1 I/O156 I/O159 DX4 DX7 I/O128 I/O129 AX0 AX1 I/O134 I/O133 AX6 AX5 I/O139 I/O138 BX3 BX2 I/O114 I/O142 O2 BX6 VCC GND GND VCC VCC GND GND GND VCC VCC GND VCC GND GND VCC VCC GND GND VCC VCC I/O98 M2 GND I/O91 L3 I/O90 L2 VCC I/O89 L1 I/O96 M0 I/O88 L0 GND I/O67 I3 I/O66 I2 GND I/O93 L5 I/O92 L4 CLK1 VCC I/O69 I5 I/O80 K0 GND I/O94 L6 I/O64 I0 I/O95 L7 VCC GND GND GND I/O123 I/O121 I/O100 P3 P1 M4 GND VCC GND VCC VCC GND I/O87 K7 I/O85 K5 I/O82 K2 I/O118 I/O109 I/O110 I/O111 I/O124 I/O122 I/O101 O6 N5 N6 N7 P4 P2 M5 I/O108 I/O107 I/O104 I/O127 I/O120 I/O102 N4 N3 N0 P7 P0 M6 I/O106 I/O105 I/O126 I/O125 I/O103 N2 N1 P6 P5 M7 CLK2 I/O99 M3 I/O97 M1 TMS I/O79 J7 I/O86 K6 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block m4a3.384.192_256bga ispMACH 4A Family 57 256-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/192) Bottom View 256-Ball fpBGA 16 A 15 14 13 12 11 10 9 8 I/O1 A1 I/O0 A0 7 I/O3 A3 I/O5 A5 I/O6 A6 GND I/O2 A2 I/O4 A4 VCC 6 CLK0 I/O7 A7 I/O20 C4 VCC I/O16 C0 I/O19 C3 I/O33 F1 I/O43 G3 I/O30 E6 I/O25 E1 I/O68 L4 I/O83 O3 VCC I/O79 N7 I/O76 N4 I/O73 N1 6 5 I/O17 C1 I/O18 C2 I/O22 C6 GND 4 I/O21 C5 I/O8 B0 I/O15 B7 VCC 3 I/O21 C7 I/O11 B3 I/O14 B6 I/O9 B1 I/O36 F4 I/O32 F0 I/O42 G2 I/O28 E4 I/O65 L1 I/O71 L7 I/O51 J3 I/O60 K4 TCK 2 I/O10 B2 I/O13 B5 TDI I/O38 F6 I/O35 F3 I/O46 G6 I/O41 G1 I/O27 E3 I/O64 L0 I/O70 L6 I/O52 J4 I/O55 J7 I/O56 K0 I/O57 K1 I/O59 K3 I/O62 K6 2 1 I/O12 B4 N/C I/O39 F7 I/O37 F5 I/O47 G7 I/O45 G5 I/O31 E7 I/O26 E2 I/O66 L2 I/O48 J0 I/O49 J1 I/O50 J2 I/O53 J5 I/O54 J6 I/O58 K2 I/O61 K5 1 A I/O159 I/O181 I/O180 I/O177 I/O174 I/O172 I/O191 I/O186 KX7 OX5 OX4 OX1 NX6 NX4 PX7 PX2 I/O157 I/O158 I/O182 I/O179 I/O175 I/O173 I/O168 I/O187 KX5 KX6 OX6 OX3 NX7 NX5 NX0 PX3 I/O155 I/O156 KX3 KX4 I/O150 I/O151 JX6 JX7 I/O148 JX4 N/C N/C B B C I/O183 I/O178 I/O170 I/O171 I/O189 I/O184 OX7 OX2 NX2 NX3 PX5 PX0 GND GND VCC GND VCC GND C D TDO I/O154 KX2 D E VCC I/O152 I/O153 I/O190 KX0 KX1 PX6 CLK3 I/O188 PX4 N/C I/O34 F2 I/O44 G4 I/O40 G0 I/O29 E5 I/O24 E0 I/O67 L3 I/O69 L5 GND I/O84 O4 I/O81 O1 I/O78 N6 5 GND E F I/O144 I/O149 I/O147 JX0 JX5 JX3 I/O163 I/O166 I/O165 LX3 LX6 LX5 I/O160 I/O162 I/O161 LX0 LX2 LX1 I/O122 I/O123 I/O124 EX2 EX3 EX4 I/O127 I/O136 I/O137 EX7 GX0 GX1 I/O140 I/O141 I/O143 GX4 GX5 GX7 GND I/O146 I/O145 I/O176 I/O169 I/O185 JX2 JX1 OX0 NX1 PX1 I/O164 I/O167 LX4 LX7 I/O120 I/O121 EX0 EX1 I/O126 I/O125 EX6 EX5 I/O139 I/O138 GX3 GX2 I/O130 I/O142 FX2 GX6 VCC GND GND VCC F G VCC GND G H GND GND VCC VCC GND VCC H J GND GND VCC VCC GND GND J K VCC VCC I/O98 AX2 GND I/O91 P3 I/O90 P2 VCC I/O89 P1 I/O96 AX0 I/O88 P0 9 GND I/O75 N3 I/O74 N2 GND I/O93 P5 I/O92 P4 CLK1 8 VCC I/O77 N5 I/O80 O0 GND I/O94 P6 I/O72 N0 I/O95 P7 7 VCC K L GND GND L M I/O128 I/O129 I/O131 FX0 FX1 FX3 N I/O132 I/O133 I/O135 FX4 FX5 FX7 GND I/O115 I/O113 I/O100 CX3 CX1 AX4 GND VCC GND VCC M VCC GND I/O87 O7 I/O85 O5 I/O82 O2 4 N P I/O134 I/O109 I/O110 I/O111 I/O116 I/O114 I/O101 FX6 BX5 BX6 BX7 CX4 CX2 AX5 I/O108 I/O107 I/O104 I/O119 I/O112 I/O102 BX4 BX3 BX0 CX7 CX0 AX6 I/O106 I/O105 I/O118 I/O117 I/O103 BX2 BX1 CX6 CX5 AX7 16 15 14 13 12 CLK2 11 I/O99 AX3 I/O97 AX1 10 TMS I/O63 K7 I/O86 O6 3 P R R T T PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block m4a3.512.192_256bga 58 ispMACH 4A Family 388-BALL fpBGA CONNECTION DIAGRAM (M4A3-512/256) Bottom View 388-Ball fpBGA 22 A B C D E F G H J K L 21 20 19 18 17 16 15 14 13 12 11 I/O0 A0 I/O2 A2 10 I/O5 A5 CLK0 I/O7 A7 I/O24 D0 9 I/O6 A6 I/O26 D2 I/O25 D1 VCC 8 I/O27 D3 I/O29 D5 I/O16 C0 I/O19 C3 7 I/O30 D6 I/O31 D7 I/O18 C2 I/O21 C5 6 I/O17 C1 I/O20 C4 I/O23 C7 VCC 5 I/O22 C6 I/O9 B1 I/O11 B3 I/O14 B6 4 I/O8 B0 I/O12 B4 I/O15 B7 GND I/O45 F5 VCC 3 I/O10 B2 I/O13 B5 GND I/O46 F6 I/O42 F2 I/O55 G7 I/O51 G3 I/O38 E6 I/O35 E3 I/O62 H6 I/O59 H3 I/O65 I1 I/O71 I7 I/O92 L4 I/O95 L7 I/O76 J4 I/O80 K0 I/O83 K3 I/O87 K7 2 N/C GND I/O47 F7 I/O43 F3 I/O40 F0 I/O52 G4 I/O49 G1 I/O37 E5 I/O34 E2 I/O61 H5 I/O57 H1 I/O66 I2 I/O70 I6 I/O91 L3 I/O94 L6 I/O73 J1 I/O77 J5 I/O81 K1 I/O84 K4 TMS 1 GND TDI I/O44 F4 I/O41 F1 I/O54 G6 I/O50 G2 I/O39 E7 I/O36 E4 I/O32 E0 I/O60 H4 I/O56 H0 I/O64 I0 I/O68 I4 I/O90 L2 I/O93 L5 I/O72 J0 I/O75 J3 I/O79 J7 I/O82 K2 I/O85 K5 TCK GND I/O243 I/O240 I/O241 I/O236 I/O231 I/O228 I/O226 I/O255 I/O251 I/O248 OX3 OX0 OX1 NX4 MX7 MX4 MX2 PX7 PX3 PX0 N/C GND I/O245 I/O242 I/O238 I/O234 I/O232 I/O229 I/O224 I/O253 I/O249 OX5 OX2 NX6 NX2 NX0 MX5 MX0 PX5 PX1 A B C D E F G H J K L M N P R T U V W Y AA AB I/O213 TDO KX5 GND I/O247 I/O244 I/O239 I/O235 I/O230 I/O227 CLK3 I/O250 I/O11 OX7 OX4 NX7 NX3 MX6 MX3 PX2 A1 I/O3 A3 I/O210 I/O212 I/O215 GND I/O246 VCC I/O237 I/O233 VCC I/O254 VCC KX2 KX4 KX7 OX6 NX5 NX1 PX6 I/O207 I/O209 I/O211 I/O214 JX7 KX1 KX3 KX6 I/O203 I/O205 I/O208 VCC JX3 JX5 KX0 I/O200 I/O202 I/O204 I/O206 JX0 JX2 JX4 JX6 I/O221 I/O222 I/O223 I/O201 LX5 LX6 LX7 JX1 I/O218 I/O219 I/O220 VCC LX2 LX3 LX4 I/O197 I/O198 I/O199 I/O216 IX5 IX6 IX7 LX0 I/O192 I/O194 I/O195 I/O196 IX0 IX2 IX3 IX4 VCC VCC N/C VCC N/C GND N/C GND GND GND GND GND GND GND GND N/C I/O225 I/O252 MX1 PX4 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND I/O4 A4 GND GND GND GND GND GND GND GND I/O28 D4 GND GND GND GND GND GND GND GND N/C GND GND GND GND GND GND GND GND N/C VCC N/C GND GND GND GND GND GND N/C VCC VCC VCC N/C I/O33 E1 I/O58 H2 I/O69 I5 I/O89 L1 N/C VCC VCC I/O53 G5 I/O48 G0 VCC I/O63 H7 VCC I/O67 I3 I/O88 L0 VCC I/O74 J2 I/O78 J6 VCC I/O86 K6 I/O217 GND LX1 I/O193 GND IX1 I/O186 GND HX2 I/O162 GND EX2 N/C VCC VCC GND N/C VCC M I/O184 I/O185 I/O187 VCC HX0 HX1 HX3 N P R T U V I/O188 I/O189 I/O191 I/O190 HX4 HX5 HX7 HX6 I/O160 I/O161 I/O163 VCC EX0 EX1 EX3 I/O164 I/O165 I/O166 I/O177 EX4 EX5 EX6 GX1 I/O167 I/O176 I/O179 I/O181 EX7 GX0 GX3 GX5 I/O178 I/O180 I/O183 VCC GX2 GX4 GX7 I/O182 GX6 N/C I/O169 I/O172 FX1 FX4 I/O152 I/O131 I/O122 I/O98 DX0 AX3 P2 M2 W I/O168 I/O170 I/O173 GND I/O143 VCC I/O150 I/O145 VCC I/O153 I/O123 VCC FX0 FX2 FX5 BX7 CX6 CX1 DX1 P3 Y I/O96 M0 VCC I/O104 I/O111 VCC I/O119 GND N0 N7 O7 I/O171 I/O174 GND I/O141 I/O138 I/O136 I/O147 I/O158 I/O156 CLK2 I/O132 I/O121 I/O125 I/O99 I/O101 I/O106 I/O110 I/O115 I/O118 GND FX3 FX6 BX5 BX2 BX0 CX3 DX6 DX4 AX4 P1 P5 M3 M5 N2 N6 O3 O6 AA I/O175 GND I/O142 I/O140 I/O151 I/O149 I/O144 I/O157 I/O154 I/O134 I/O130 I/O128 CLK1 I/O127 I/O100 I/O103 I/O108 I/O109 I/O113 I/O116 GND FX7 BX6 BX4 CX7 CX5 CX0 DX5 DX2 AX6 AX2 AX0 P7 M4 M7 N4 N5 O1 O4 AB GND N/C I/O139 I/O137 I/O148 I/O146 I/O159 I/O155 I/O135 I/O133 I/O129 I/O120 I/O124 I/O126 I/O97 I/O102 I/O105 I/O107 I/O112 I/O114 I/O117 GND BX3 BX1 CX4 CX2 DX7 DX3 AX7 AX5 AX1 P0 P4 P6 M1 M6 N1 N3 O0 O2 O5 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 PIN DESIGNATIONS CLK GND I I/O N/C VCC TDI TCK TMS TDO TRST ENABLE = = = = = = = = = = = = Clock Ground Input Input/Output No Connect Supply Voltage Test Data In Test Clock Test Mode Select Test Data Out Test Reset Program C 7 I/O Cell PAL Block m4a3.512.256_388bga ispMACH 4A Family 59 ispMACH 4A PRODUCT ORDERING INFORMATION ispMACH 4A Devices Commercial and Industrial - 3.3V and 5V Lattice programmable logic products are available with several ordering options.The order number (Valid Combination) is formed by a combination of: M4A3256 / 128 -7 Y C FAMILY TYPE M4A3- = ispMACH 4A Family Low Voltage Advanced Feature (3.3-V VCC) M4A5- = ispMACH 4A Family Advanced Feature (5-V VCC) MACROCELL DENSITY 32=32 Macrocells192 64=64 Macrocells256 96=96 Macrocells384 128=128 Macrocells512 48 = 48-pin TQFP for M4A3-32/32 or M4A3-64/32 M4A5-32/32 or M4A5-64/32 = = = = 192 Macrocells 256 Macrocells 384 Macrocells 512 Macrocells OPERATING CONDITIONS C = Commercial (0C to +70C) I = Industrial (-40C to +85C) PACKAGE TYPE A = Ball Grid Array (BGA) J = Plastic Leaded Chip Carrier (PLCC) V = Thin Quad Flat Pack (TQFP) Y = Plastic Quad Flat Pack (PQFP) FA = Fine-pitch Ball Grid Array (fpBGA) CA = Chip-array Ball Grid Array (caBGA) SPEED -5 =5.0 ns tPD -55 =5.5 ns tPD -6 =6.0 ns tPD -65 =6.5 ns tPD -7 =7.5 ns tPD -10 =10 ns tPD -12 =12 ns tPD -14 =14 ns tPD I/Os /32 /48 /64 /96 /128 /160 /192 /256 = = = = = = = = 32 I/Os in 44-pin PLCC, 44-pin TQFP or 48-pin TQFP 48 I/Os in 100-pin TQFP 64 I/Os in 100-pin TQFP, 100-pin PQFP, or 100-ball caBGA 96 I/Os in 144-pin TQFP or 144-ball fpBGA 128 I/Os in 208-pin PQFP, 256-ball BGA or 256-ball fpBGA 160 I/Os in 208-pin PQFP 192 I/Os in 256-ball BGA or 256-ball fpBGA 256 I/Os in 388-ball fpBGA M4A3-32/32 M4A3-64/32 M4A3-64/64 M4A3-96/48 M4A3-128/64 M4A3-192/96 M4A3-256/128 M4A3-256/1601 M4A3-256/1921 M4A3-384/160 M4A3-384/192 M4A3-512/160 M4A3-512/192 M4A3-512/256 3.3V Commercial Combinations -5, -7, -10 JC, VC, VC48 JC, VC, VC48 VC -55, -7, -10 VC YC, VC, CAC -6, -7, -10 VC, FAC -55, -65, -7, -10 YC, AC, FAC YC -7, -10 FAC YC -65, -10, -12 AC, FAC YC -7, -10, -12 FAC FAC M4A3-32/32 M4A3-64/32 M4A3-64/64 M4A3-96/48 M4A3-128/64 M4A3-192/96 M4A3-256/128 M4A3-256/160 M4A3-256/192 M4A3-384/160 M4A3-384/192 M4A3-512/160 M4A3-512/192 M4A3-512/256 3.3V Industrial Combinations JI, VI, VI48 JI, VI, VI48 VI -7, -10, -12 VI YI, VI, CAI VI, FAI -7, -10, -12 YI, AI, FAI YI -10, -12 FAI YI AI, FAI YI -10, -12, -14 FAI FAI 1. Contact Factory for 6.5ns availability 60 ispMACH 4A Family M4A5-32/32 M4A5-64/32 M4A5-96/48 M4A5-128/64 M4A5-192/96 M4A5-256/128 5V Commercial Combinations -5, -7, -10, JC, VC, VC48 JC, VC, VC48 -55, -7, -10 VC YC, VC -6, -7, -10 VC -65, -7, -10 YC, AC M4A5-32/32 M4A5-64/32 M4A5-96/48 M4A5-128/64 M4A5-192/96 M4A5-256/128 5V Industrial Combinations -7, -10, -12 JI, VI, VI48 JI, VI, VI48 -7, -10, -12 VI YI, VI -7, -10, -12 VI -10, -12 YI, AI Most ispMACH devices are dual-marked with both Commercial and Industrial grades.The Industrial speed grade is slower, i.e., M4A3256/128-7YC-10YI Valid Combinations Valid Combinations list configurations planned to be supported in volume for this device. Consult the local Lattice sales office to confirm availability of specific valid combinations and to check on newly released combinations. Copyright (c) 2000 Lattice Semiconductor. All rights reserved. ispMACH 4A Family 61 62 ispMACH 4A Family |
Price & Availability of M4A3-3232-10JI
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